| /hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/include/ |
| D | CanEXCEL_Ip.h | 494 …pe Canexcel_Ip_SetTDCOffsetFD(uint8 Instance, boolean TDCEnable, boolean TDCMEnable, uint8 Offset);
508 …pe Canexcel_Ip_SetTDCOffsetXL(uint8 Instance, boolean TDCEnable, boolean TDCMEnable, uint8 Offset);
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| /hal_nxp-latest/s32/drivers/s32ze/Can_CANEXCEL/src/ |
| D | CanEXCEL_Ip.c | 147 …id CanXL_SetTDCOffsetFD(CANXL_SIC_Type * base, boolean TDCEnable, boolean TDCMEnable, uint8 Offset) in CanXL_SetTDCOffsetFD() argument
151 … ? 1UL : 0UL) | CANXL_SIC_BTDCC_FTDMDIS(TDCMEnable ? 1UL : 0UL) | CANXL_SIC_BTDCC_FTDCOFF(Offset)); in CanXL_SetTDCOffsetFD()
159 …id CanXL_SetTDCOffsetXL(CANXL_SIC_Type * base, boolean TDCEnable, boolean TDCMEnable, uint8 Offset) in CanXL_SetTDCOffsetXL() argument
163 … ? 1UL : 0UL) | CANXL_SIC_BTDCC_XTDMDIS(TDCMEnable ? 1UL : 0UL) | CANXL_SIC_BTDCC_XTDCOFF(Offset)); in CanXL_SetTDCOffsetXL()
1922 …ype Canexcel_Ip_SetTDCOffsetFD(uint8 Instance, boolean TDCEnable, boolean TDCMEnable, uint8 Offset) in Canexcel_Ip_SetTDCOffsetFD() argument
1934 CanXL_SetTDCOffsetFD(Base, TDCEnable, TDCMEnable, Offset); in Canexcel_Ip_SetTDCOffsetFD()
1948 …ype Canexcel_Ip_SetTDCOffsetXL(uint8 Instance, boolean TDCEnable, boolean TDCMEnable, uint8 Offset) in Canexcel_Ip_SetTDCOffsetXL() argument
1961 CanXL_SetTDCOffsetXL(Base, TDCEnable, TDCMEnable, Offset); in Canexcel_Ip_SetTDCOffsetXL()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/gcc/ |
| D | MIMX8UD7xxxxx_cm33_flash.ld | 32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 …
40 …* entry point of m33 in flexspi0 nor flash = flexspi0 start address + 1st Image Container Offset +…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/gcc/ |
| D | MIMX8UD5xxxxx_cm33_flash.ld | 32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 …
40 …* entry point of m33 in flexspi0 nor flash = flexspi0 start address + 1st Image Container Offset +…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/gcc/ |
| D | MIMX8US5xxxxx_cm33_flash.ld | 32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 …
40 …* entry point of m33 in flexspi0 nor flash = flexspi0 start address + 1st Image Container Offset +…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/gcc/ |
| D | MIMX8US3xxxxx_cm33_flash.ld | 32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 …
40 …* entry point of m33 in flexspi0 nor flash = flexspi0 start address + 1st Image Container Offset +…
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/gcc/ |
| D | MIMX8UD3xxxxx_cm33_flash.ld | 32 /* Memory region from [0x04000000-0x04000FFF] is reserved(1st Image Container Offset is 0x1000 = 4 …
40 …* entry point of m33 in flexspi0 nor flash = flexspi0 start address + 1st Image Container Offset +…
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/include/ |
| D | Adc_Sar_Ip.h | 764 const uint8 Offset);
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| /hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/include/ |
| D | Gmac_Ip.h | 817 Gmac_Ip_SysTimeCorrOffsetType Offset,
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| /hal_nxp-latest/s32/drivers/s32ze/EthSwt_NETC/include/ |
| D | Netc_EthSwt_Ip.h | 1208 Std_ReturnType Netc_EthSwt_Ip_CorrectPtpClk( uint8 SwitchIdx, sint64 Offset );
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| /hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/src/ |
| D | Gmac_Ip.c | 3100 Gmac_Ip_SysTimeCorrOffsetType Offset, in Gmac_Ip_SetSysTimeCorr() argument
3115 if (((uint32)Offset) != 0U) in Gmac_Ip_SetSysTimeCorr()
3127 …Base->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE = GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(Offset) | in Gmac_Ip_SetSysTimeCorr()
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| /hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-connectivity-framework/platform/Common/ |
| D | fwk_platform_mcuboot_ota.ch | 23 * FW_UPDATE_STORAGE_OFFSET: Offset address of the firmware update storage
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/src/ |
| D | Adc_Sar_Ip.c | 5173 const uint8 Offset) in Adc_Sar_Ip_SetUserGainAndOffset() argument
5192 RegVal = ADC_AE_USER_OFFSET(Offset); in Adc_Sar_Ip_SetUserGainAndOffset()
5201 RegVal = ADC_USER_OFFSET(Offset); in Adc_Sar_Ip_SetUserGainAndOffset()
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| /hal_nxp-latest/s32/drivers/s32ze/EthSwt_NETC/src/ |
| D | Netc_EthSwt_Ip.c | 8699 Std_ReturnType Netc_EthSwt_Ip_CorrectPtpClk( uint8 SwitchIdx, sint64 Offset ) argument
8712 … NewOffset = OriginOffset + ((uint64) (Offset)); /* the offset could be positive or negative */
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