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Searched refs:OTPC_RWC_WR_ALL1S_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h42443 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
42449 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h42413 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
42419 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h53270 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
53276 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
DMCXN546_cm33_core1.h53270 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
53276 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h53270 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
53276 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
DMCXN547_cm33_core1.h53270 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
53276 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h54005 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
54011 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
DMCXN947_cm33_core0.h54005 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
54011 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h54005 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
54011 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)
DMCXN946_cm33_core1.h54005 #define OTPC_RWC_WR_ALL1S_MASK (0x1000U) macro
54011 … (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK)