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Searched refs:OTFAD_SR_RRAM_MASK (Results 1 – 25 of 32) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/otfad/
Dfsl_otfad.c150 regAccessMode = (uint8_t)((base->SR & OTFAD_SR_RRAM_MASK) >> OTFAD_SR_RRAM_SHIFT); in OTFAD_SetEncryptionConfig()
201 regAccessMode = (uint8_t)((base->SR & OTFAD_SR_RRAM_MASK) >> OTFAD_SR_RRAM_SHIFT); in OTFAD_GetEncryptionConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h18233 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
18239 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h16722 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
16728 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT685S_cm33.h23640 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
23646 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h22265 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
22271 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h22266 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
22272 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h21985 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
21991 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h23640 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
23646 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h27943 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
27949 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT595S_cm33.h35131 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
35137 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h33504 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
33510 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h35130 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
35136 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h59017 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
59023 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT1175_cm7.h58115 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
58121 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h57591 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
57597 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT1165_cm4.h58493 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
58499 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h58115 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
58121 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h62401 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
62407 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT1166_cm7.h61499 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
61505 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h62922 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
62928 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT1173_cm7.h62020 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
62026 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h62023 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
62029 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h72690 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
72696 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
DMIMXRT1176_cm4.h73592 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
73598 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h68162 #define OTFAD_SR_RRAM_MASK (0x10000000U) macro
68168 … (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)

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