| /hal_nxp-latest/mcux/mcux-sdk/components/video/display/it6161/ |
| D | fsl_it6161.h | 106 #define HDMITX_SetI2C_Byte(handle, RegAddr, Mask, Value) \ argument
107 IT6161_I2C_ModifyReg(handle, HDMI_TX_ADDR, RegAddr, Mask, Value)
116 #define HDMITX_CEC_SetI2C_Byte(handle, RegAddr, Mask, Value) \ argument
117 IT6161_I2C_ModifyReg(handle, HDMI_TX_CEC_ADDR, RegAddr, Mask, Value)
123 #define MIPIRX_SetI2C_Byte(handle, RegAddr, Mask, Value) \ argument
124 IT6161_I2C_ModifyReg(handle, MIPI_RX_ADDR, RegAddr, Mask, Value)
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_HwAccess.h | 884 uint32 Mask in Qspi_Ip_EnableInt() argument
887 BaseAddr->RSER |= Mask; in Qspi_Ip_EnableInt()
895 uint32 Mask in Qspi_Ip_DisableInt() argument
898 BaseAddr->RSER &= ~Mask; in Qspi_Ip_DisableInt()
906 uint32 Mask in Qspi_Ip_ClearIntFlag() argument
909 BaseAddr->FR = Mask; in Qspi_Ip_ClearIntFlag()
1164 uint8 Mask) in Qspi_Ip_Sfp_SetTgMask() argument
1170 RegValue |= QuadSPI_TGMDAD_MASK(Mask); in Qspi_Ip_Sfp_SetTgMask()
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| D | Qspi_Ip_Types.h | 381 uint8 Mask; member
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| /hal_nxp-latest/s32/drivers/s32ze/Uart/include/ |
| D | Linflexd_Uart_Ip_HwAccess.h | 657 uint32 Mask; in Linflexd_Uart_Ip_SetTxDataBuffer2Bytes() local
664 Mask = LINFLEXD_BDRL_DATA0_MASK | LINFLEXD_BDRL_DATA1_MASK; in Linflexd_Uart_Ip_SetTxDataBuffer2Bytes()
665 Base->BDRL = ((uint32)DataTemp & Mask); in Linflexd_Uart_Ip_SetTxDataBuffer2Bytes()
693 uint32 Mask = LINFLEXD_BDRM_DATA4_MASK | LINFLEXD_BDRM_DATA5_MASK; in Linflexd_Uart_Ip_GetRxDataBuffer2Bytes() local
694 Data = (uint16)(Base->BDRM & Mask); in Linflexd_Uart_Ip_GetRxDataBuffer2Bytes()
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/ |
| D | Qspi_Ip_HwAccess.h | 1208 uint32 Mask in Qspi_Ip_EnableInt() argument
1211 BaseAddr->RSER |= Mask; in Qspi_Ip_EnableInt()
1219 uint32 Mask in Qspi_Ip_DisableInt() argument
1222 BaseAddr->RSER &= ~Mask; in Qspi_Ip_DisableInt()
1230 uint32 Mask in Qspi_Ip_ClearIntFlag() argument
1233 BaseAddr->FR = Mask; in Qspi_Ip_ClearIntFlag()
1578 uint8 Mask) in Qspi_Ip_Sfp_SetTgMask() argument
1584 RegValue |= QuadSPI_TGMDAD_MASK(Mask); in Qspi_Ip_Sfp_SetTgMask()
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| D | Qspi_Ip_Types.h | 384 uint8 Mask; member
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/src/ |
| D | Adc_Sar_Ip.c | 375 const uint32 * const Mask);
377 const uint32 * const Mask);
1541 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx); in Adc_Sar_CheckAndCallEocNotification() local
1551 Cimr = (CIMR(AdcAEBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1558 Cimr = (CIMR(AdcBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1561 Ceocfr = ((*CEOCFRAddr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1566 *CEOCFRAddr = Mask; in Adc_Sar_CheckAndCallEocNotification()
1596 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx); in Adc_Sar_CheckAndCallWorrNotification() local
1611 Cwenr = (CWENR(AdcAEBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallWorrNotification()
1620 Cwenr = (CWENR(AdcBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallWorrNotification()
[all …]
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/src/ |
| D | Adc_Sar_Ip.c | 371 const uint32 * const Mask);
373 const uint32 * const Mask);
1435 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx); in Adc_Sar_CheckAndCallEocNotification() local
1445 Cimr = (CIMR(AdcAEBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1452 Cimr = (CIMR(AdcBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1455 Ceocfr = ((*CEOCFRAddr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1460 *CEOCFRAddr = Mask; in Adc_Sar_CheckAndCallEocNotification()
1490 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx); in Adc_Sar_CheckAndCallWorrNotification() local
1504 Cwenr = (CWENR(AdcAEBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallWorrNotification()
1513 Cwenr = (CWENR(AdcBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallWorrNotification()
[all …]
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| /hal_nxp-latest/s32/drivers/s32k3/Mcl/src/ |
| D | Lcu_Ip_Hw_Access.c | 405 uint8 Mask = 1U << HwOutput; in HwAcc_Lcu_AsyncGetCombineForceInput() local
409 ReturnValue = (uint8)((ReturnValue & Mask) >> HwOutput); in HwAcc_Lcu_AsyncGetCombineForceInput()
597 uint8 Mask = 1U << HwOutput; in HwAcc_Lcu_AsyncGetCombineForce() local
601 *Value = (uint8)((ReturnValue & Mask) >> HwOutput); in HwAcc_Lcu_AsyncGetCombineForce()
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| /hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-usb/host/class/ |
| D | usb_host_cdc_ecm.h | 90 uint8_t *Mask; member
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| D | usb_host_cdc_ecm.c | 180 *p++ = param->Mask[i]; in USB_HostCdcEcmPowerManagementPatternFilterData()
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| /hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/include/ |
| D | Gmac_Ip.h | 649 const uint8 Mask,
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| /hal_nxp-latest/s32/drivers/s32k3/Eth_GMAC/src/ |
| D | Gmac_Ip.c | 2546 const uint8 Mask, in Gmac_Ip_SetAddrPerfectFilter() argument
2580 Base->MAC_ADDRESS1_HIGH |= GMAC_MAC_ADDRESS1_HIGH_MBC(Mask); in Gmac_Ip_SetAddrPerfectFilter()
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| /hal_nxp-latest/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Controller.c | 1823 Qspi_Ip_Sfp_SetTgMask(baseAddr, Index, userConfigPtr->SfpCfg.Tg[Index].Mask); in Qspi_Ip_Sfp_Configure_Mdad()
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| /hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/ |
| D | Qspi_Ip_Controller.c | 2161 Qspi_Ip_Sfp_SetTgMask(baseAddr, MdadInstance, userConfigPtr->SfpCfg.Tg[MdadInstance].Mask); in Qspi_Ip_Sfp_SetMdadConfig()
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