Home
last modified time | relevance | path

Searched refs:LPCMP_RRCR1_RR_CH0EN_MASK (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPCMP.h357 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
360 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h17138 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
17144 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h17138 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
17144 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h17138 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
17144 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h17138 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
17144 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h23354 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
23360 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h23354 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
23360 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h23354 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
23360 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h23358 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
23364 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h23358 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
23364 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h23358 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
23364 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h36571 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
36577 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h36541 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
36547 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h46762 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
46768 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
DMCXN546_cm33_core1.h46762 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
46768 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h46762 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
46768 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
DMCXN547_cm33_core1.h46762 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
46768 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h47219 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
47225 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
DMCXN947_cm33_core0.h47219 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
47225 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h47219 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
47225 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)
DMCXN946_cm33_core1.h47219 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) macro
47225 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK)