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Searched refs:LPCMP_RRCR0_RR_NSAM_SHIFT (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPCMP.h344 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
346 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h17063 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
17070 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h17063 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
17070 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h17063 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
17070 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h17063 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
17070 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h23279 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
23286 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h23279 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
23286 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h23279 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
23286 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h23283 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
23290 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h23283 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
23290 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h23283 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
23290 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h36496 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
36503 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h36466 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
36473 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h46687 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
46694 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
DMCXN546_cm33_core1.h46687 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
46694 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h46687 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
46694 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
DMCXN547_cm33_core1.h46687 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
46694 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h47144 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
47151 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
DMCXN947_cm33_core0.h47144 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
47151 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h47144 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
47151 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…
DMCXN946_cm33_core1.h47144 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) macro
47151 …R0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCM…