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Searched refs:LPCMP_RRCR0_RR_EN_MASK (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/lpcmp/
Dfsl_lpcmp.h498 base->RRCR0 |= LPCMP_RRCR0_RR_EN_MASK; in LPCMP_EnableRoundRobinMode()
502 base->RRCR0 &= ~LPCMP_RRCR0_RR_EN_MASK; in LPCMP_EnableRoundRobinMode()
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPCMP.h338 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
341 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h17024 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
17030 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h17024 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
17030 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h17024 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
17030 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h17024 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
17030 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h23240 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
23246 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h23240 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
23246 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h23240 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
23246 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h23244 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
23250 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h23244 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
23250 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h23244 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
23250 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h36479 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
36485 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h36449 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
36455 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h46670 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
46676 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
DMCXN546_cm33_core1.h46670 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
46676 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h46670 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
46676 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
DMCXN547_cm33_core1.h46670 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
46676 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h47105 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
47111 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
DMCXN947_cm33_core0.h47105 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
47111 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h47105 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
47111 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)
DMCXN946_cm33_core1.h47105 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) macro
47111 … (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK)