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Searched refs:LMEM (Results 1 – 25 of 128) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm4/
Dfsl_cache.c31 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) in L1CACHE_EnableCodeCache()
37 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_EnableCodeCache()
51 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_DisableCodeCache()
62 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; in L1CACHE_InvalidateCodeCache()
65 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in L1CACHE_InvalidateCodeCache()
70 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); in L1CACHE_InvalidateCodeCache()
91 …pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_… in L1CACHE_InvalidateCodeCacheByRange()
92 LMEM->PCCLCR = pccReg; in L1CACHE_InvalidateCodeCacheByRange()
97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
100 while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) in L1CACHE_InvalidateCodeCacheByRange()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm4/
Dfsl_cache.c31 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) in L1CACHE_EnableCodeCache()
37 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_EnableCodeCache()
51 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_DisableCodeCache()
62 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; in L1CACHE_InvalidateCodeCache()
65 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in L1CACHE_InvalidateCodeCache()
70 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); in L1CACHE_InvalidateCodeCache()
91 …pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_… in L1CACHE_InvalidateCodeCacheByRange()
92 LMEM->PCCLCR = pccReg; in L1CACHE_InvalidateCodeCacheByRange()
97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
100 while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) in L1CACHE_InvalidateCodeCacheByRange()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm4/
Dfsl_cache.c31 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) in L1CACHE_EnableCodeCache()
37 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_EnableCodeCache()
51 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_DisableCodeCache()
62 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; in L1CACHE_InvalidateCodeCache()
65 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in L1CACHE_InvalidateCodeCache()
70 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); in L1CACHE_InvalidateCodeCache()
91 …pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_… in L1CACHE_InvalidateCodeCacheByRange()
92 LMEM->PCCLCR = pccReg; in L1CACHE_InvalidateCodeCacheByRange()
97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
100 while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) in L1CACHE_InvalidateCodeCacheByRange()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/lmem/
Dfsl_cache.c31 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) in L1CACHE_EnableCodeCache()
37 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_EnableCodeCache()
51 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_DisableCodeCache()
62 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; in L1CACHE_InvalidateCodeCache()
65 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in L1CACHE_InvalidateCodeCache()
70 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); in L1CACHE_InvalidateCodeCache()
91 …pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_… in L1CACHE_InvalidateCodeCacheByRange()
92 LMEM->PCCLCR = pccReg; in L1CACHE_InvalidateCodeCacheByRange()
97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
100 while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) in L1CACHE_InvalidateCodeCacheByRange()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm4/
Dfsl_cache.c31 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) in L1CACHE_EnableCodeCache()
37 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_EnableCodeCache()
51 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_DisableCodeCache()
62 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; in L1CACHE_InvalidateCodeCache()
65 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in L1CACHE_InvalidateCodeCache()
70 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); in L1CACHE_InvalidateCodeCache()
91 …pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_… in L1CACHE_InvalidateCodeCacheByRange()
92 LMEM->PCCLCR = pccReg; in L1CACHE_InvalidateCodeCacheByRange()
97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
100 while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) in L1CACHE_InvalidateCodeCacheByRange()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm4/
Dfsl_cache.c31 if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) in L1CACHE_EnableCodeCache()
37 LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_EnableCodeCache()
51 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in L1CACHE_DisableCodeCache()
62 LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; in L1CACHE_InvalidateCodeCache()
65 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in L1CACHE_InvalidateCodeCache()
70 LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); in L1CACHE_InvalidateCodeCache()
91 …pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_… in L1CACHE_InvalidateCodeCacheByRange()
92 LMEM->PCCLCR = pccReg; in L1CACHE_InvalidateCodeCacheByRange()
97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
100 while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) in L1CACHE_InvalidateCodeCacheByRange()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
Dsystem_MIMX8DX3_cm4.c104 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
105 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
107 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
111 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
115 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
116 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
118 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
122 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
Dsystem_MIMX8QX1_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
Dsystem_MIMX8DX2_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
Dsystem_MIMX8DX6_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
Dsystem_MIMX8QX5_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
Dsystem_MIMX8QM6_cm4_core0.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { in SystemInit()
112 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
116 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
119 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { in SystemInit()
122 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
Dsystem_MIMX8QM6_cm4_core1.c105 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
106 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
108 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { in SystemInit()
111 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
115 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
116 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
118 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { in SystemInit()
121 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/
Dsystem_MIMX8QX4_cm4.c104 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
105 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
107 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
111 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
115 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
116 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
118 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
122 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
Dsystem_MIMX8QX6_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
Dsystem_MIMX8QX2_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/
Dsystem_MIMX8DX5_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
Dsystem_MIMX8DX4_cm4.c104 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
105 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
107 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
111 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
115 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
116 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
118 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
122 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/
Dsystem_MIMX8UX5_cm4.c107 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
108 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
110 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
114 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
119 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
121 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
125 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/
Dsystem_MIMX8UX6_cm4.c107 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
108 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
110 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
114 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
119 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
121 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
125 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
Dsystem_MIMX8QX3_cm4.c104 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
105 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
107 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
111 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
115 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
116 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
118 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
122 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
Dsystem_MIMX8DX1_cm4.c106 LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; in SystemInit()
107 LMEM->PCCCR |= LMEM_PCCCR_GO_MASK; in SystemInit()
109 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0UL) in SystemInit()
113 LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); in SystemInit()
117 LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; in SystemInit()
118 LMEM->PSCCR |= LMEM_PSCCR_GO_MASK; in SystemInit()
120 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0UL) in SystemInit()
124 LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1160/
Dboard.c511 if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) in BOARD_ConfigMPU()
514 LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; in BOARD_ConfigMPU()
516 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in BOARD_ConfigMPU()
520 LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); in BOARD_ConfigMPU()
522 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in BOARD_ConfigMPU()
526 if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) in BOARD_ConfigMPU()
529 LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; in BOARD_ConfigMPU()
531 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) in BOARD_ConfigMPU()
535 LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); in BOARD_ConfigMPU()
537 LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; in BOARD_ConfigMPU()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/
Dboard.c511 if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) in BOARD_ConfigMPU()
514 LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; in BOARD_ConfigMPU()
516 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in BOARD_ConfigMPU()
520 LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); in BOARD_ConfigMPU()
522 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in BOARD_ConfigMPU()
526 if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) in BOARD_ConfigMPU()
529 LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; in BOARD_ConfigMPU()
531 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) in BOARD_ConfigMPU()
535 LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); in BOARD_ConfigMPU()
537 LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; in BOARD_ConfigMPU()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/
Dboard.c511 if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) in BOARD_ConfigMPU()
514 LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; in BOARD_ConfigMPU()
516 while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) in BOARD_ConfigMPU()
520 LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); in BOARD_ConfigMPU()
522 LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; in BOARD_ConfigMPU()
526 if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) in BOARD_ConfigMPU()
529 LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; in BOARD_ConfigMPU()
531 while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) in BOARD_ConfigMPU()
535 LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); in BOARD_ConfigMPU()
537 LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; in BOARD_ConfigMPU()
[all …]

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