511     if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR))  in BOARD_ConfigMPU()
514         LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;  in BOARD_ConfigMPU()
516         while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)  in BOARD_ConfigMPU()
520         LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);  in BOARD_ConfigMPU()
522         LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;  in BOARD_ConfigMPU()
526     if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR))  in BOARD_ConfigMPU()
529         LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;  in BOARD_ConfigMPU()
531         while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)  in BOARD_ConfigMPU()
535         LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);  in BOARD_ConfigMPU()
537         LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;  in BOARD_ConfigMPU()
638     LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;  in BOARD_ConfigMPU()
640     while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U)  in BOARD_ConfigMPU()
644     LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);  in BOARD_ConfigMPU()
646     LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;  in BOARD_ConfigMPU()
650     LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;  in BOARD_ConfigMPU()
652     while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U)  in BOARD_ConfigMPU()
656     LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);  in BOARD_ConfigMPU()
658     LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;  in BOARD_ConfigMPU()