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Searched refs:LDOCTLA (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/vbat/
Dfsl_vbat.c75 base->LDOCTLA |= VBAT_LDOCTLA_BG_EN_MASK; in VBAT_EnableBandgap()
85 base->LDOCTLA &= ~VBAT_LDOCTLA_BG_EN_MASK; in VBAT_EnableBandgap()
116 base->LDOCTLA |= VBAT_LDOCTLA_LDO_EN_MASK; in VBAT_EnableBackupSRAMRegulator()
135 base->LDOCTLA &= ~VBAT_LDOCTLA_LDO_EN_MASK; in VBAT_EnableBackupSRAMRegulator()
Dfsl_vbat.h256 return (bool)((base->LDOCTLA & VBAT_LDOCTLA_BG_EN_MASK) == VBAT_LDOCTLA_BG_EN_MASK); in VBAT_CheckBandgapEnabled()
273 base->LDOCTLA |= VBAT_LDOCTLA_REFRESH_EN_MASK; in VBAT_EnableBandgapRefreshMode()
277 base->LDOCTLA &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; in VBAT_EnableBandgapRefreshMode()
/hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_vbat/
Dfsl_vbat.c127 base->LDOCTLA |= VBAT_LDOCTLA_BG_EN_MASK; in VBAT_EnableBandgap()
138 base->LDOCTLA &= ~VBAT_LDOCTLA_BG_EN_MASK; in VBAT_EnableBandgap()
170 base->LDOCTLA |= VBAT_LDOCTLA_LDO_EN_MASK; in VBAT_EnableBackupSRAMRegulator()
191 base->LDOCTLA &= ~VBAT_LDOCTLA_LDO_EN_MASK; in VBAT_EnableBackupSRAMRegulator()
Dfsl_vbat.h755 return (bool)((base->LDOCTLA & VBAT_LDOCTLA_BG_EN_MASK) == VBAT_LDOCTLA_BG_EN_MASK); in VBAT_CheckBandgapEnabled()
773 base->LDOCTLA |= VBAT_LDOCTLA_REFRESH_EN_MASK; in VBAT_EnableBandgapRefreshMode()
778 base->LDOCTLA &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; in VBAT_EnableBandgapRefreshMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h43144 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h45313 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h67020 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h66978 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h50319 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
DMCXW727C_cm33_core1.h56121 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h87706 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
DMCXN546_cm33_core1.h87706 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h87706 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
DMCXN547_cm33_core1.h87706 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h90372 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
DMCXN947_cm33_core0.h90372 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h90372 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member
DMCXN946_cm33_core1.h90372 __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ member