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Searched refs:IPTXFCR (Results 1 – 25 of 110) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi_edma.c193 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferEDMA()
209 …handle->count = (uint8_t)((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_… in FLEXSPI_TransferEDMA()
319 if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortEDMA()
353 else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountEDMA()
Dfsl_flexspi.c349 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; in FLEXSPI_Init()
350 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK((uint32_t)config->txWatermark / 8U - 1U); in FLEXSPI_Init()
657 …uint32_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SH… in FLEXSPI_WriteBlocking()
855 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferBlocking()
979 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferNonBlocking()
1157 …txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1U; in FLEXSPI_TransferHandleIRQ()
Dfsl_flexspi_dma.c175 …8U * ((uint8_t)(((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + … in FLEXSPI_WriteDataDMA()
544 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferDMA()
601 if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortDMA()
634 else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountDMA()
Dfsl_flexspi.h500 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; in FLEXSPI_EnableTxDMA()
504 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; in FLEXSPI_EnableTxDMA()
563 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_ResetFifos()
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/flexspi_dma3/
Dfsl_flexspi_edma.c209 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; in FLEXSPI_TransferEDMA()
225 …handle->count = (uint8_t)((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_… in FLEXSPI_TransferEDMA()
335 if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferAbortEDMA()
369 else if ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXDMAEN_MASK) != 0x00U) in FLEXSPI_TransferGetTransferCountEDMA()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1180/jlinkscript/
Devkmimxrt1180_cm33.jlinkscript314 MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR
Devkmimxrt1180_cm7.jlinkscript314 MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7156 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
DMIMXRT685S_cm33.h13133 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h15933 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13419 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13133 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h13457 __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h13457 __IO uint32_t IPTXFCR; /**< IP Transmit FIFO Control, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h13002 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19272 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19252 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21381 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20229 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h19596 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21383 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h21014 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h21758 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h26871 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h26869 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ member

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