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Searched refs:IOMUXC_GPR (Results 1 – 25 of 131) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1020/
Dclock_config.c401 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
403 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
405 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
407 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
409 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
411 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
414 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
417 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
422 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
424 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1024/
Dclock_config.c401 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
403 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
405 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
407 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
409 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
411 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
414 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
417 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
422 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
424 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/
Dclock_config.c845 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
847 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); in BOARD_BootClockRUN()
849 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
851 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
853 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
856 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
858 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
860 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN()
862 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
864 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/
Dclock_config.c845 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
847 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); in BOARD_BootClockRUN()
849 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
851 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
853 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
856 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
858 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
860 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN()
862 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
864 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1160/
Dclock_config.c787 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
789 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); in BOARD_BootClockRUN()
791 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
793 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
795 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
798 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
800 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
802 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN()
804 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
806 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1015/
Dclock_config.c346 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
348 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
350 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
352 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
354 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
356 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
358 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
360 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
651 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN_400M()
653 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN_400M()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbimxrt1050/
Dclock_config.c469 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
471 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
473 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
475 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
477 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
479 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
482 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
485 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
490 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
492 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1060/
Dclock_config.c488 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
492 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
494 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
496 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
498 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
500 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
504 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1060/
Dclock_config.c488 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
492 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
494 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
496 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
498 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
500 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
504 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1064/
Dclock_config.c490 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
492 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
494 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
496 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
498 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
500 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
504 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
508 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkcmimxrt1060/
Dclock_config.c487 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
489 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
491 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
493 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
495 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
497 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
499 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
501 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
503 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
505 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1040/
Dclock_config.c459 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
461 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
463 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
465 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); in BOARD_BootClockRUN()
467 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
469 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
471 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
473 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
475 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
893 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN_600M()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1010/
Dclock_config.c331 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN()
333 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN()
335 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN()
337 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); in BOARD_BootClockRUN()
339 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); in BOARD_BootClockRUN()
341 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
343 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
619 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); in BOARD_BootClockRUN_400M()
621 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); in BOARD_BootClockRUN_400M()
623 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); in BOARD_BootClockRUN_400M()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()
Dfsl_flexram_allocate.c81 tempGPR17 = IOMUXC_GPR->GPR17; in FLEXRAM_AllocateRam()
82 tempGPR18 = IOMUXC_GPR->GPR18; in FLEXRAM_AllocateRam()
84 …IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU… in FLEXRAM_AllocateRam()
85 …IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) … in FLEXRAM_AllocateRam()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()
Dfsl_flexram_allocate.c81 tempGPR17 = IOMUXC_GPR->GPR17; in FLEXRAM_AllocateRam()
82 tempGPR18 = IOMUXC_GPR->GPR18; in FLEXRAM_AllocateRam()
84 …IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU… in FLEXRAM_AllocateRam()
85 …IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) … in FLEXRAM_AllocateRam()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()
Dfsl_flexram_allocate.c81 tempGPR17 = IOMUXC_GPR->GPR17; in FLEXRAM_AllocateRam()
82 tempGPR18 = IOMUXC_GPR->GPR18; in FLEXRAM_AllocateRam()
84 …IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU… in FLEXRAM_AllocateRam()
85 …IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) … in FLEXRAM_AllocateRam()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()
Dfsl_flexram_allocate.c81 tempGPR17 = IOMUXC_GPR->GPR17; in FLEXRAM_AllocateRam()
82 tempGPR18 = IOMUXC_GPR->GPR18; in FLEXRAM_AllocateRam()
84 …IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU… in FLEXRAM_AllocateRam()
85 …IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) … in FLEXRAM_AllocateRam()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()
Dfsl_flexram_allocate.c81 tempGPR17 = IOMUXC_GPR->GPR17; in FLEXRAM_AllocateRam()
82 tempGPR18 = IOMUXC_GPR->GPR18; in FLEXRAM_AllocateRam()
84 …IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU… in FLEXRAM_AllocateRam()
85 …IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) … in FLEXRAM_AllocateRam()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_soc_mipi_csi2rx.c34 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
38 IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; in MIPI_CSI2RX_SoftwareReset()
47 IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | in MIPI_CSI2RX_InitInterface()
62 IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; in MIPI_CSI2RX_InitInterface()
67 …IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR… in MIPI_CSI2RX_DeinitInterface()

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