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Searched refs:INTR (Results 1 – 25 of 126) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.c666 while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) in FLEXSPI_WriteBlocking()
717 base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; in FLEXSPI_WriteBlocking()
748 … while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) in FLEXSPI_ReadBlocking()
764 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_ReadBlocking()
779 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_ReadBlocking()
824 base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; in FLEXSPI_ReadBlocking()
848 …base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK… in FLEXSPI_TransferBlocking()
886 while (0UL == (base->INTR & FLEXSPI_INTR_IPCMDDONE_MASK)) in FLEXSPI_TransferBlocking()
893 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_TransferBlocking()
972 …base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK… in FLEXSPI_TransferNonBlocking()
[all …]
Dfsl_flexspi_edma.c186 …base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MAS… in FLEXSPI_TransferEDMA()
294 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_TransferEDMA()
Dfsl_flexspi.h606 return base->INTR; in FLEXSPI_GetInterruptStatusFlags()
617 base->INTR = mask; in FLEXSPI_ClearInterruptStatusFlags()
Dfsl_flexspi_dma.c537 …base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MAS… in FLEXSPI_TransferDMA()
575 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_TransferDMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/sdma/
Dfsl_sdma.c448 status = base->INTR; in SDMA_ResetModule()
1057 val = (SDMAARM->INTR) >> 1U; in SDMA_DriverIRQHandler()
1079 val = (SDMAARM1->INTR) >> 1U; in SDMA1_DriverIRQHandler()
1101 val = (SDMAARM2->INTR) >> 1U; in SDMA2_DriverIRQHandler()
1124 val = (SDMAARM3->INTR) >> 1U; in SDMA3_DriverIRQHandler()
Dfsl_sdma.h564 return base->INTR; in SDMA_GetChannelInterruptStatus()
575 base->INTR = mask; in SDMA_ClearChannelInterruptStatus()
/hal_nxp-latest/mcux/mcux-sdk/drivers/semc/
Dfsl_semc.c267 while ((base->INTR & (uint32_t)SEMC_INTR_IPCMDDONE_MASK) == 0x00U) in SEMC_IsIPCommandDone()
272 base->INTR |= SEMC_INTR_IPCMDDONE_MASK; in SEMC_IsIPCommandDone()
275 if ((base->INTR & (uint32_t)SEMC_INTR_IPCMDERR_MASK) != 0x00U) in SEMC_IsIPCommandDone()
277 base->INTR |= SEMC_INTR_IPCMDERR_MASK; in SEMC_IsIPCommandDone()
1211 base->INTR |= SEMC_INTR_IPCMDDONE_MASK; in SEMC_SendIPCommand()
Dfsl_semc.h798 return (base->INTR != 0x00U) ? true : false; in SEMC_GetStatusFlag()
811 base->INTR |= mask; in SEMC_ClearStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/flexspi_dma3/
Dfsl_flexspi_edma.c202 …base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MAS… in FLEXSPI_TransferEDMA()
310 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_TransferEDMA()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1160/
Dclock_config.c58 while ((SEMC->INTR & 0x3) == 0) in UpdateSemcClock()
60 SEMC->INTR = 0x3; in UpdateSemcClock()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/
Dclock_config.c58 while ((SEMC->INTR & 0x3) == 0) in UpdateSemcClock()
60 SEMC->INTR = 0x3; in UpdateSemcClock()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/
Dclock_config.c58 while ((SEMC->INTR & 0x3) == 0) in UpdateSemcClock()
60 SEMC->INTR = 0x3; in UpdateSemcClock()
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h32064 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ member
32109 #define SDMAARM_INTR_REG(base) ((base)->INTR)
32486 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ member
32507 #define SDMABP_INTR_REG(base) ((base)->INTR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19235 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
33220 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19255 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
33241 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20212 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
34804 __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21364 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
36021 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h20997 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
39070 __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21366 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
39431 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h21741 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
36905 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h26854 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
46503 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h26852 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
46501 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h26852 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
46501 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h26854 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
46503 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h22600 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ member
41106 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ member

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