Lines Matching refs:INTR
666 while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag)) in FLEXSPI_WriteBlocking()
717 base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; in FLEXSPI_WriteBlocking()
748 … while (0U == ((status = base->INTR) & (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) in FLEXSPI_ReadBlocking()
764 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_ReadBlocking()
779 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_ReadBlocking()
824 base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; in FLEXSPI_ReadBlocking()
848 …base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK… in FLEXSPI_TransferBlocking()
886 while (0UL == (base->INTR & FLEXSPI_INTR_IPCMDDONE_MASK)) in FLEXSPI_TransferBlocking()
893 result = FLEXSPI_CheckAndClearError(base, base->INTR); in FLEXSPI_TransferBlocking()
972 …base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK… in FLEXSPI_TransferNonBlocking()
1075 status = base->INTR; in FLEXSPI_TransferHandleIRQ()
1136 base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag; in FLEXSPI_TransferHandleIRQ()
1141 base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag; in FLEXSPI_TransferHandleIRQ()
1198 base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag; in FLEXSPI_TransferHandleIRQ()