1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_INTERFACE_CONFIGURATION.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_INTERFACE_CONFIGURATION 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_INTERFACE_CONFIGURATION_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_INTERFACE_CONFIGURATION_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- INTERFACE_CONFIGURATION Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup INTERFACE_CONFIGURATION_Peripheral_Access_Layer INTERFACE_CONFIGURATION Peripheral Access Layer 68 * @{ 69 */ 70 71 /** INTERFACE_CONFIGURATION - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t D_PORT_RID; /**< DMSS AXI Read ID Control, offset: 0x0 */ 74 __IO uint32_t D_PORT_WID; /**< DMSS AXI Port Write ID Control, offset: 0x4 */ 75 uint8_t RESERVED_0[24]; 76 __IO uint32_t D_ADD0_START; /**< DMSS ADD0 START, offset: 0x20 */ 77 __IO uint32_t D_ADD0_ATT0; /**< DMSS ADD0 ATT0, offset: 0x24 */ 78 __IO uint32_t D_ADD0_ATT1; /**< DMSS ADD0 ATT1, offset: 0x28 */ 79 uint8_t RESERVED_1[4]; 80 __IO uint32_t D_ADD1_START; /**< DMSS ADD1 START, offset: 0x30 */ 81 __IO uint32_t D_ADD1_ATT0; /**< DMSS ADD1 ATT0, offset: 0x34 */ 82 __IO uint32_t D_ADD1_ATT1; /**< DMSS ADD1 ATT1, offset: 0x38 */ 83 uint8_t RESERVED_2[4]; 84 __IO uint32_t D_ADD2_START; /**< DMSS ADD2 START, offset: 0x40 */ 85 __IO uint32_t D_ADD2_ATT0; /**< DMSS ADD2 ATT0, offset: 0x44 */ 86 __IO uint32_t D_ADD2_ATT1; /**< DMSS ADD2 ATT1, offset: 0x48 */ 87 uint8_t RESERVED_3[4]; 88 __IO uint32_t D_ADD3_START; /**< DMSS ADD3 START, offset: 0x50 */ 89 __IO uint32_t D_ADD3_ATT0; /**< DMSS ADD3 ATT0, offset: 0x54 */ 90 __IO uint32_t D_ADD3_ATT1; /**< DMSS ADD3 ATT1, offset: 0x58 */ 91 uint8_t RESERVED_4[4]; 92 __IO uint32_t D_ADD4_START; /**< DMSS ADD4 START, offset: 0x60 */ 93 __IO uint32_t D_ADD4_ATT0; /**< DMSS ADD4 ATT0, offset: 0x64 */ 94 __IO uint32_t D_ADD4_ATT1; /**< DMSS ADD4 ATT1, offset: 0x68 */ 95 uint8_t RESERVED_5[4]; 96 __IO uint32_t D_ADD5_START; /**< DMSS ADD5 START, offset: 0x70 */ 97 __IO uint32_t D_ADD5_ATT0; /**< DMSS ADD5 ATT0, offset: 0x74 */ 98 __IO uint32_t D_ADD5_ATT1; /**< DMSS ADD5 ATT1, offset: 0x78 */ 99 uint8_t RESERVED_6[4]; 100 __IO uint32_t D_ADD6_START; /**< DMSS ADD6 START, offset: 0x80 */ 101 __IO uint32_t D_ADD6_ATT0; /**< DMSS ADD6 ATT0, offset: 0x84 */ 102 __IO uint32_t D_ADD6_ATT1; /**< DMSS ADD6 ATT1, offset: 0x88 */ 103 uint8_t RESERVED_7[4]; 104 __IO uint32_t D_ADD7_START; /**< DMSS ADD7 START, offset: 0x90 */ 105 __IO uint32_t D_ADD7_ATT0; /**< DMSS ADD7 ATT0, offset: 0x94 */ 106 __IO uint32_t D_ADD7_ATT1; /**< DMSS ADD7 ATT1, offset: 0x98 */ 107 } INTERFACE_CONFIGURATION_Type, *INTERFACE_CONFIGURATION_MemMapPtr; 108 109 /** Number of instances of the INTERFACE_CONFIGURATION module. */ 110 #define INTERFACE_CONFIGURATION_INSTANCE_COUNT (1u) 111 112 /* INTERFACE_CONFIGURATION - Peripheral instance base addresses */ 113 /** Peripheral CEVA_SPF2__INTERFACE_CONFIGURATION base address */ 114 #define IP_CEVA_SPF2__INTERFACE_CONFIGURATION_BASE (0x24400900u) 115 /** Peripheral CEVA_SPF2__INTERFACE_CONFIGURATION base pointer */ 116 #define IP_CEVA_SPF2__INTERFACE_CONFIGURATION ((INTERFACE_CONFIGURATION_Type *)IP_CEVA_SPF2__INTERFACE_CONFIGURATION_BASE) 117 /** Array initializer of INTERFACE_CONFIGURATION peripheral base addresses */ 118 #define IP_INTERFACE_CONFIGURATION_BASE_ADDRS { IP_CEVA_SPF2__INTERFACE_CONFIGURATION_BASE } 119 /** Array initializer of INTERFACE_CONFIGURATION peripheral base pointers */ 120 #define IP_INTERFACE_CONFIGURATION_BASE_PTRS { IP_CEVA_SPF2__INTERFACE_CONFIGURATION } 121 122 /* ---------------------------------------------------------------------------- 123 -- INTERFACE_CONFIGURATION Register Masks 124 ---------------------------------------------------------------------------- */ 125 126 /*! 127 * @addtogroup INTERFACE_CONFIGURATION_Register_Masks INTERFACE_CONFIGURATION Register Masks 128 * @{ 129 */ 130 131 /*! @name D_PORT_RID - DMSS AXI Read ID Control */ 132 /*! @{ */ 133 134 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_MASK (0xFU) 135 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_SHIFT (0U) 136 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_WIDTH (4U) 137 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_MASK) 138 139 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_MASK (0xF0U) 140 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_SHIFT (4U) 141 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_WIDTH (4U) 142 #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_MASK) 143 144 #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_MASK (0xF0000U) 145 #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_SHIFT (16U) 146 #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_WIDTH (4U) 147 #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_MASK) 148 149 #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_MASK (0xF00000U) 150 #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_SHIFT (20U) 151 #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_WIDTH (4U) 152 #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_MASK) 153 /*! @} */ 154 155 /*! @name D_PORT_WID - DMSS AXI Port Write ID Control */ 156 /*! @{ */ 157 158 #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_MASK (0xFU) 159 #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_SHIFT (0U) 160 #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_WIDTH (4U) 161 #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_MASK) 162 163 #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_MASK (0xF0U) 164 #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_SHIFT (4U) 165 #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_WIDTH (4U) 166 #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_MASK) 167 168 #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_MASK (0xF0000U) 169 #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_SHIFT (16U) 170 #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_WIDTH (4U) 171 #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_MASK) 172 173 #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_MASK (0xF00000U) 174 #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_SHIFT (20U) 175 #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_WIDTH (4U) 176 #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_MASK) 177 /*! @} */ 178 179 /*! @name D_ADD0_START - DMSS ADD0 START */ 180 /*! @{ */ 181 182 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_MASK (0xFFFFFU) 183 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_SHIFT (0U) 184 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_WIDTH (20U) 185 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_MASK) 186 187 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_MASK (0xFF00000U) 188 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_SHIFT (20U) 189 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_WIDTH (8U) 190 #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_MASK) 191 192 #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_MASK (0x20000000U) 193 #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_SHIFT (29U) 194 #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_WIDTH (1U) 195 #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_MASK) 196 /*! @} */ 197 198 /*! @name D_ADD0_ATT0 - DMSS ADD0 ATT0 */ 199 /*! @{ */ 200 201 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_MASK (0x10000U) 202 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_SHIFT (16U) 203 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_WIDTH (1U) 204 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_MASK) 205 206 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_MASK (0xE0000U) 207 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_SHIFT (17U) 208 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_WIDTH (3U) 209 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_MASK) 210 211 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_MASK (0xF000000U) 212 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_SHIFT (24U) 213 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_WIDTH (4U) 214 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_MASK) 215 216 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_MASK (0xF0000000U) 217 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_SHIFT (28U) 218 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_WIDTH (4U) 219 #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_MASK) 220 /*! @} */ 221 222 /*! @name D_ADD0_ATT1 - DMSS ADD0 ATT1 */ 223 /*! @{ */ 224 225 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_MASK (0x1U) 226 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_SHIFT (0U) 227 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_WIDTH (1U) 228 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_MASK) 229 230 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_MASK (0x1EU) 231 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_SHIFT (1U) 232 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_WIDTH (4U) 233 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_MASK) 234 235 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_MASK (0x1E0U) 236 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_SHIFT (5U) 237 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_WIDTH (4U) 238 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_MASK) 239 240 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_MASK (0x1E00U) 241 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_SHIFT (9U) 242 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_WIDTH (4U) 243 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_MASK) 244 245 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_MASK (0x1E000U) 246 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_SHIFT (13U) 247 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_WIDTH (4U) 248 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_MASK) 249 250 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_MASK (0x1C0000U) 251 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_SHIFT (18U) 252 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_WIDTH (3U) 253 #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_MASK) 254 /*! @} */ 255 256 /*! @name D_ADD1_START - DMSS ADD1 START */ 257 /*! @{ */ 258 259 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_MASK (0xFFFFFU) 260 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_SHIFT (0U) 261 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_WIDTH (20U) 262 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_MASK) 263 264 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_MASK (0xFF00000U) 265 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_SHIFT (20U) 266 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_WIDTH (8U) 267 #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_MASK) 268 269 #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_MASK (0x10000000U) 270 #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_SHIFT (28U) 271 #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_WIDTH (1U) 272 #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_MASK) 273 274 #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_MASK (0x20000000U) 275 #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_SHIFT (29U) 276 #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_WIDTH (1U) 277 #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_MASK) 278 /*! @} */ 279 280 /*! @name D_ADD1_ATT0 - DMSS ADD1 ATT0 */ 281 /*! @{ */ 282 283 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_MASK (0x10000U) 284 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_SHIFT (16U) 285 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_WIDTH (1U) 286 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_MASK) 287 288 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_MASK (0xE0000U) 289 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_SHIFT (17U) 290 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_WIDTH (3U) 291 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_MASK) 292 293 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_MASK (0xF000000U) 294 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_SHIFT (24U) 295 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_WIDTH (4U) 296 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_MASK) 297 298 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_MASK (0xF0000000U) 299 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_SHIFT (28U) 300 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_WIDTH (4U) 301 #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_MASK) 302 /*! @} */ 303 304 /*! @name D_ADD1_ATT1 - DMSS ADD1 ATT1 */ 305 /*! @{ */ 306 307 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_MASK (0x1U) 308 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_SHIFT (0U) 309 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_WIDTH (1U) 310 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_MASK) 311 312 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_MASK (0x1EU) 313 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_SHIFT (1U) 314 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_WIDTH (4U) 315 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_MASK) 316 317 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_MASK (0x1E0U) 318 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_SHIFT (5U) 319 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_WIDTH (4U) 320 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_MASK) 321 322 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_MASK (0x1E00U) 323 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_SHIFT (9U) 324 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_WIDTH (4U) 325 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_MASK) 326 327 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_MASK (0x1E000U) 328 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_SHIFT (13U) 329 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_WIDTH (4U) 330 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_MASK) 331 332 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_MASK (0x1C0000U) 333 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_SHIFT (18U) 334 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_WIDTH (3U) 335 #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_MASK) 336 /*! @} */ 337 338 /*! @name D_ADD2_START - DMSS ADD2 START */ 339 /*! @{ */ 340 341 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_MASK (0xFFFFFU) 342 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_SHIFT (0U) 343 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_WIDTH (20U) 344 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_MASK) 345 346 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_MASK (0xFF00000U) 347 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_SHIFT (20U) 348 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_WIDTH (8U) 349 #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_MASK) 350 351 #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_MASK (0x10000000U) 352 #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_SHIFT (28U) 353 #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_WIDTH (1U) 354 #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_MASK) 355 356 #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_MASK (0x20000000U) 357 #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_SHIFT (29U) 358 #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_WIDTH (1U) 359 #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_MASK) 360 /*! @} */ 361 362 /*! @name D_ADD2_ATT0 - DMSS ADD2 ATT0 */ 363 /*! @{ */ 364 365 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_MASK (0x10000U) 366 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_SHIFT (16U) 367 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_WIDTH (1U) 368 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_MASK) 369 370 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_MASK (0xE0000U) 371 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_SHIFT (17U) 372 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_WIDTH (3U) 373 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_MASK) 374 375 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_MASK (0xF000000U) 376 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_SHIFT (24U) 377 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_WIDTH (4U) 378 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_MASK) 379 380 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_MASK (0xF0000000U) 381 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_SHIFT (28U) 382 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_WIDTH (4U) 383 #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_MASK) 384 /*! @} */ 385 386 /*! @name D_ADD2_ATT1 - DMSS ADD2 ATT1 */ 387 /*! @{ */ 388 389 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_MASK (0x1U) 390 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_SHIFT (0U) 391 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_WIDTH (1U) 392 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_MASK) 393 394 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_MASK (0x1EU) 395 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_SHIFT (1U) 396 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_WIDTH (4U) 397 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_MASK) 398 399 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_MASK (0x1E0U) 400 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_SHIFT (5U) 401 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_WIDTH (4U) 402 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_MASK) 403 404 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_MASK (0x1E00U) 405 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_SHIFT (9U) 406 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_WIDTH (4U) 407 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_MASK) 408 409 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_MASK (0x1E000U) 410 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_SHIFT (13U) 411 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_WIDTH (4U) 412 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_MASK) 413 414 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_MASK (0x1C0000U) 415 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_SHIFT (18U) 416 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_WIDTH (3U) 417 #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_MASK) 418 /*! @} */ 419 420 /*! @name D_ADD3_START - DMSS ADD3 START */ 421 /*! @{ */ 422 423 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_MASK (0xFFFFFU) 424 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_SHIFT (0U) 425 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_WIDTH (20U) 426 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_MASK) 427 428 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_MASK (0xFF00000U) 429 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_SHIFT (20U) 430 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_WIDTH (8U) 431 #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_MASK) 432 433 #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_MASK (0x10000000U) 434 #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_SHIFT (28U) 435 #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_WIDTH (1U) 436 #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_MASK) 437 438 #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_MASK (0x20000000U) 439 #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_SHIFT (29U) 440 #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_WIDTH (1U) 441 #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_MASK) 442 /*! @} */ 443 444 /*! @name D_ADD3_ATT0 - DMSS ADD3 ATT0 */ 445 /*! @{ */ 446 447 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_MASK (0x10000U) 448 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_SHIFT (16U) 449 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_WIDTH (1U) 450 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_MASK) 451 452 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_MASK (0xE0000U) 453 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_SHIFT (17U) 454 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_WIDTH (3U) 455 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_MASK) 456 457 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_MASK (0xF000000U) 458 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_SHIFT (24U) 459 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_WIDTH (4U) 460 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_MASK) 461 462 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_MASK (0xF0000000U) 463 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_SHIFT (28U) 464 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_WIDTH (4U) 465 #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_MASK) 466 /*! @} */ 467 468 /*! @name D_ADD3_ATT1 - DMSS ADD3 ATT1 */ 469 /*! @{ */ 470 471 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_MASK (0x1U) 472 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_SHIFT (0U) 473 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_WIDTH (1U) 474 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_MASK) 475 476 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_MASK (0x1EU) 477 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_SHIFT (1U) 478 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_WIDTH (4U) 479 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_MASK) 480 481 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_MASK (0x1E0U) 482 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_SHIFT (5U) 483 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_WIDTH (4U) 484 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_MASK) 485 486 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_MASK (0x1E00U) 487 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_SHIFT (9U) 488 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_WIDTH (4U) 489 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_MASK) 490 491 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_MASK (0x1E000U) 492 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_SHIFT (13U) 493 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_WIDTH (4U) 494 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_MASK) 495 496 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_MASK (0x1C0000U) 497 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_SHIFT (18U) 498 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_WIDTH (3U) 499 #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_MASK) 500 /*! @} */ 501 502 /*! @name D_ADD4_START - DMSS ADD4 START */ 503 /*! @{ */ 504 505 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_MASK (0xFFFFFU) 506 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_SHIFT (0U) 507 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_WIDTH (20U) 508 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_MASK) 509 510 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_MASK (0xFF00000U) 511 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_SHIFT (20U) 512 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_WIDTH (8U) 513 #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_MASK) 514 515 #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_MASK (0x10000000U) 516 #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_SHIFT (28U) 517 #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_WIDTH (1U) 518 #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_MASK) 519 520 #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_MASK (0x20000000U) 521 #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_SHIFT (29U) 522 #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_WIDTH (1U) 523 #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_MASK) 524 /*! @} */ 525 526 /*! @name D_ADD4_ATT0 - DMSS ADD4 ATT0 */ 527 /*! @{ */ 528 529 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_MASK (0x10000U) 530 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_SHIFT (16U) 531 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_WIDTH (1U) 532 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_MASK) 533 534 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_MASK (0xE0000U) 535 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_SHIFT (17U) 536 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_WIDTH (3U) 537 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_MASK) 538 539 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_MASK (0xF000000U) 540 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_SHIFT (24U) 541 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_WIDTH (4U) 542 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_MASK) 543 544 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_MASK (0xF0000000U) 545 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_SHIFT (28U) 546 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_WIDTH (4U) 547 #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_MASK) 548 /*! @} */ 549 550 /*! @name D_ADD4_ATT1 - DMSS ADD4 ATT1 */ 551 /*! @{ */ 552 553 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_MASK (0x1U) 554 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_SHIFT (0U) 555 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_WIDTH (1U) 556 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_MASK) 557 558 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_MASK (0x1EU) 559 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_SHIFT (1U) 560 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_WIDTH (4U) 561 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_MASK) 562 563 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_MASK (0x1E0U) 564 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_SHIFT (5U) 565 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_WIDTH (4U) 566 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_MASK) 567 568 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_MASK (0x1E00U) 569 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_SHIFT (9U) 570 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_WIDTH (4U) 571 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_MASK) 572 573 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_MASK (0x1E000U) 574 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_SHIFT (13U) 575 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_WIDTH (4U) 576 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_MASK) 577 578 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_MASK (0x1C0000U) 579 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_SHIFT (18U) 580 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_WIDTH (3U) 581 #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_MASK) 582 /*! @} */ 583 584 /*! @name D_ADD5_START - DMSS ADD5 START */ 585 /*! @{ */ 586 587 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_MASK (0xFFFFFU) 588 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_SHIFT (0U) 589 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_WIDTH (20U) 590 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_MASK) 591 592 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_MASK (0xFF00000U) 593 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_SHIFT (20U) 594 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_WIDTH (8U) 595 #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_MASK) 596 597 #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_MASK (0x10000000U) 598 #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_SHIFT (28U) 599 #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_WIDTH (1U) 600 #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_MASK) 601 602 #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_MASK (0x20000000U) 603 #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_SHIFT (29U) 604 #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_WIDTH (1U) 605 #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_MASK) 606 /*! @} */ 607 608 /*! @name D_ADD5_ATT0 - DMSS ADD5 ATT0 */ 609 /*! @{ */ 610 611 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_MASK (0x10000U) 612 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_SHIFT (16U) 613 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_WIDTH (1U) 614 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_MASK) 615 616 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_MASK (0xE0000U) 617 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_SHIFT (17U) 618 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_WIDTH (3U) 619 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_MASK) 620 621 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_MASK (0xF000000U) 622 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_SHIFT (24U) 623 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_WIDTH (4U) 624 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_MASK) 625 626 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_MASK (0xF0000000U) 627 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_SHIFT (28U) 628 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_WIDTH (4U) 629 #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_MASK) 630 /*! @} */ 631 632 /*! @name D_ADD5_ATT1 - DMSS ADD5 ATT1 */ 633 /*! @{ */ 634 635 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_MASK (0x1U) 636 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_SHIFT (0U) 637 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_WIDTH (1U) 638 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_MASK) 639 640 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_MASK (0x1EU) 641 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_SHIFT (1U) 642 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_WIDTH (4U) 643 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_MASK) 644 645 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_MASK (0x1E0U) 646 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_SHIFT (5U) 647 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_WIDTH (4U) 648 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_MASK) 649 650 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_MASK (0x1E00U) 651 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_SHIFT (9U) 652 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_WIDTH (4U) 653 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_MASK) 654 655 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_MASK (0x1E000U) 656 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_SHIFT (13U) 657 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_WIDTH (4U) 658 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_MASK) 659 660 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_MASK (0x1C0000U) 661 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_SHIFT (18U) 662 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_WIDTH (3U) 663 #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_MASK) 664 /*! @} */ 665 666 /*! @name D_ADD6_START - DMSS ADD6 START */ 667 /*! @{ */ 668 669 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_MASK (0xFFFFFU) 670 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_SHIFT (0U) 671 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_WIDTH (20U) 672 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_MASK) 673 674 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_MASK (0xFF00000U) 675 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_SHIFT (20U) 676 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_WIDTH (8U) 677 #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_MASK) 678 679 #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_MASK (0x10000000U) 680 #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_SHIFT (28U) 681 #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_WIDTH (1U) 682 #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_MASK) 683 684 #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_MASK (0x20000000U) 685 #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_SHIFT (29U) 686 #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_WIDTH (1U) 687 #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_MASK) 688 /*! @} */ 689 690 /*! @name D_ADD6_ATT0 - DMSS ADD6 ATT0 */ 691 /*! @{ */ 692 693 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_MASK (0x10000U) 694 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_SHIFT (16U) 695 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_WIDTH (1U) 696 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_MASK) 697 698 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_MASK (0xE0000U) 699 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_SHIFT (17U) 700 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_WIDTH (3U) 701 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_MASK) 702 703 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_MASK (0xF000000U) 704 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_SHIFT (24U) 705 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_WIDTH (4U) 706 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_MASK) 707 708 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_MASK (0xF0000000U) 709 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_SHIFT (28U) 710 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_WIDTH (4U) 711 #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_MASK) 712 /*! @} */ 713 714 /*! @name D_ADD6_ATT1 - DMSS ADD6 ATT1 */ 715 /*! @{ */ 716 717 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_MASK (0x1U) 718 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_SHIFT (0U) 719 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_WIDTH (1U) 720 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_MASK) 721 722 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_MASK (0x1EU) 723 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_SHIFT (1U) 724 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_WIDTH (4U) 725 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_MASK) 726 727 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_MASK (0x1E0U) 728 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_SHIFT (5U) 729 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_WIDTH (4U) 730 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_MASK) 731 732 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_MASK (0x1E00U) 733 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_SHIFT (9U) 734 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_WIDTH (4U) 735 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_MASK) 736 737 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_MASK (0x1E000U) 738 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_SHIFT (13U) 739 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_WIDTH (4U) 740 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_MASK) 741 742 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_MASK (0x1C0000U) 743 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_SHIFT (18U) 744 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_WIDTH (3U) 745 #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_MASK) 746 /*! @} */ 747 748 /*! @name D_ADD7_START - DMSS ADD7 START */ 749 /*! @{ */ 750 751 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_MASK (0xFFFFFU) 752 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_SHIFT (0U) 753 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_WIDTH (20U) 754 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_MASK) 755 756 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_MASK (0xFF00000U) 757 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_SHIFT (20U) 758 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_WIDTH (8U) 759 #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_MASK) 760 761 #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_MASK (0x10000000U) 762 #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_SHIFT (28U) 763 #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_WIDTH (1U) 764 #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_MASK) 765 766 #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_MASK (0x20000000U) 767 #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_SHIFT (29U) 768 #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_WIDTH (1U) 769 #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_MASK) 770 /*! @} */ 771 772 /*! @name D_ADD7_ATT0 - DMSS ADD7 ATT0 */ 773 /*! @{ */ 774 775 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_MASK (0x10000U) 776 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_SHIFT (16U) 777 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_WIDTH (1U) 778 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_MASK) 779 780 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_MASK (0xE0000U) 781 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_SHIFT (17U) 782 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_WIDTH (3U) 783 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_MASK) 784 785 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_MASK (0xF000000U) 786 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_SHIFT (24U) 787 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_WIDTH (4U) 788 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_MASK) 789 790 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_MASK (0xF0000000U) 791 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_SHIFT (28U) 792 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_WIDTH (4U) 793 #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_MASK) 794 /*! @} */ 795 796 /*! @name D_ADD7_ATT1 - DMSS ADD7 ATT1 */ 797 /*! @{ */ 798 799 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_MASK (0x1U) 800 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_SHIFT (0U) 801 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_WIDTH (1U) 802 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_MASK) 803 804 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_MASK (0x1EU) 805 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_SHIFT (1U) 806 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_WIDTH (4U) 807 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_MASK) 808 809 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_MASK (0x1E0U) 810 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_SHIFT (5U) 811 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_WIDTH (4U) 812 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_MASK) 813 814 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_MASK (0x1E00U) 815 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_SHIFT (9U) 816 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_WIDTH (4U) 817 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_MASK) 818 819 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_MASK (0x1E000U) 820 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_SHIFT (13U) 821 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_WIDTH (4U) 822 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_MASK) 823 824 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_MASK (0x1C0000U) 825 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_SHIFT (18U) 826 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_WIDTH (3U) 827 #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_MASK) 828 /*! @} */ 829 830 /*! 831 * @} 832 */ /* end of group INTERFACE_CONFIGURATION_Register_Masks */ 833 834 /*! 835 * @} 836 */ /* end of group INTERFACE_CONFIGURATION_Peripheral_Access_Layer */ 837 838 #endif /* #if !defined(S32Z2_INTERFACE_CONFIGURATION_H_) */ 839
