/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32Z2_INTERFACE_CONFIGURATION.h * @version 2.3 * @date 2024-05-03 * @brief Peripheral Access Layer for S32Z2_INTERFACE_CONFIGURATION * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32Z2_INTERFACE_CONFIGURATION_H_) /* Check if memory map has not been already included */ #define S32Z2_INTERFACE_CONFIGURATION_H_ #include "S32Z2_COMMON.h" /* ---------------------------------------------------------------------------- -- INTERFACE_CONFIGURATION Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup INTERFACE_CONFIGURATION_Peripheral_Access_Layer INTERFACE_CONFIGURATION Peripheral Access Layer * @{ */ /** INTERFACE_CONFIGURATION - Register Layout Typedef */ typedef struct { __IO uint32_t D_PORT_RID; /**< DMSS AXI Read ID Control, offset: 0x0 */ __IO uint32_t D_PORT_WID; /**< DMSS AXI Port Write ID Control, offset: 0x4 */ uint8_t RESERVED_0[24]; __IO uint32_t D_ADD0_START; /**< DMSS ADD0 START, offset: 0x20 */ __IO uint32_t D_ADD0_ATT0; /**< DMSS ADD0 ATT0, offset: 0x24 */ __IO uint32_t D_ADD0_ATT1; /**< DMSS ADD0 ATT1, offset: 0x28 */ uint8_t RESERVED_1[4]; __IO uint32_t D_ADD1_START; /**< DMSS ADD1 START, offset: 0x30 */ __IO uint32_t D_ADD1_ATT0; /**< DMSS ADD1 ATT0, offset: 0x34 */ __IO uint32_t D_ADD1_ATT1; /**< DMSS ADD1 ATT1, offset: 0x38 */ uint8_t RESERVED_2[4]; __IO uint32_t D_ADD2_START; /**< DMSS ADD2 START, offset: 0x40 */ __IO uint32_t D_ADD2_ATT0; /**< DMSS ADD2 ATT0, offset: 0x44 */ __IO uint32_t D_ADD2_ATT1; /**< DMSS ADD2 ATT1, offset: 0x48 */ uint8_t RESERVED_3[4]; __IO uint32_t D_ADD3_START; /**< DMSS ADD3 START, offset: 0x50 */ __IO uint32_t D_ADD3_ATT0; /**< DMSS ADD3 ATT0, offset: 0x54 */ __IO uint32_t D_ADD3_ATT1; /**< DMSS ADD3 ATT1, offset: 0x58 */ uint8_t RESERVED_4[4]; __IO uint32_t D_ADD4_START; /**< DMSS ADD4 START, offset: 0x60 */ __IO uint32_t D_ADD4_ATT0; /**< DMSS ADD4 ATT0, offset: 0x64 */ __IO uint32_t D_ADD4_ATT1; /**< DMSS ADD4 ATT1, offset: 0x68 */ uint8_t RESERVED_5[4]; __IO uint32_t D_ADD5_START; /**< DMSS ADD5 START, offset: 0x70 */ __IO uint32_t D_ADD5_ATT0; /**< DMSS ADD5 ATT0, offset: 0x74 */ __IO uint32_t D_ADD5_ATT1; /**< DMSS ADD5 ATT1, offset: 0x78 */ uint8_t RESERVED_6[4]; __IO uint32_t D_ADD6_START; /**< DMSS ADD6 START, offset: 0x80 */ __IO uint32_t D_ADD6_ATT0; /**< DMSS ADD6 ATT0, offset: 0x84 */ __IO uint32_t D_ADD6_ATT1; /**< DMSS ADD6 ATT1, offset: 0x88 */ uint8_t RESERVED_7[4]; __IO uint32_t D_ADD7_START; /**< DMSS ADD7 START, offset: 0x90 */ __IO uint32_t D_ADD7_ATT0; /**< DMSS ADD7 ATT0, offset: 0x94 */ __IO uint32_t D_ADD7_ATT1; /**< DMSS ADD7 ATT1, offset: 0x98 */ } INTERFACE_CONFIGURATION_Type, *INTERFACE_CONFIGURATION_MemMapPtr; /** Number of instances of the INTERFACE_CONFIGURATION module. */ #define INTERFACE_CONFIGURATION_INSTANCE_COUNT (1u) /* INTERFACE_CONFIGURATION - Peripheral instance base addresses */ /** Peripheral CEVA_SPF2__INTERFACE_CONFIGURATION base address */ #define IP_CEVA_SPF2__INTERFACE_CONFIGURATION_BASE (0x24400900u) /** Peripheral CEVA_SPF2__INTERFACE_CONFIGURATION base pointer */ #define IP_CEVA_SPF2__INTERFACE_CONFIGURATION ((INTERFACE_CONFIGURATION_Type *)IP_CEVA_SPF2__INTERFACE_CONFIGURATION_BASE) /** Array initializer of INTERFACE_CONFIGURATION peripheral base addresses */ #define IP_INTERFACE_CONFIGURATION_BASE_ADDRS { IP_CEVA_SPF2__INTERFACE_CONFIGURATION_BASE } /** Array initializer of INTERFACE_CONFIGURATION peripheral base pointers */ #define IP_INTERFACE_CONFIGURATION_BASE_PTRS { IP_CEVA_SPF2__INTERFACE_CONFIGURATION } /* ---------------------------------------------------------------------------- -- INTERFACE_CONFIGURATION Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup INTERFACE_CONFIGURATION_Register_Masks INTERFACE_CONFIGURATION Register Masks * @{ */ /*! @name D_PORT_RID - DMSS AXI Read ID Control */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_MASK (0xFU) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_LS0_ID_MASK) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_MASK (0xF0U) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_SHIFT (4U) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_LS1_ID_MASK) #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_MASK (0xF0000U) #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_DDMA_ID_MASK) #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_MASK (0xF00000U) #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_RID_QMAN_ID_MASK) /*! @} */ /*! @name D_PORT_WID - DMSS AXI Port Write ID Control */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_MASK (0xFU) #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_WB_ID_MASK) #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_MASK (0xF0U) #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_SHIFT (4U) #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_WBU_ID_MASK) #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_MASK (0xF0000U) #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_DDMA_N_WID_MASK) #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_MASK (0xF00000U) #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_SHIFT)) & INTERFACE_CONFIGURATION_D_PORT_WID_QMAN_WID_MASK) /*! @} */ /*! @name D_ADD0_START - DMSS ADD0 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD0_ATT0 - DMSS ADD0 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD0_ATT1 - DMSS ADD0 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD0_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD1_START - DMSS ADD1 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD1_ATT0 - DMSS ADD1 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD1_ATT1 - DMSS ADD1 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD1_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD2_START - DMSS ADD2 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD2_ATT0 - DMSS ADD2 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD2_ATT1 - DMSS ADD2 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD2_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD3_START - DMSS ADD3 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD3_ATT0 - DMSS ADD3 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD3_ATT1 - DMSS ADD3 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD3_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD4_START - DMSS ADD4 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD4_ATT0 - DMSS ADD4 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD4_ATT1 - DMSS ADD4 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD4_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD5_START - DMSS ADD5 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD5_ATT0 - DMSS ADD5 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD5_ATT1 - DMSS ADD5 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD5_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD6_START - DMSS ADD6 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD6_ATT0 - DMSS ADD6 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD6_ATT1 - DMSS ADD6 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD6_ATT1_DAUOL_MASK) /*! @} */ /*! @name D_ADD7_START - DMSS ADD7 START */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_MASK (0xFFFFFU) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_WIDTH (20U) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_REGION_START_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_MASK (0xFF00000U) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_SHIFT (20U) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_WIDTH (8U) #define INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_REGION_MID_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_MASK (0x10000000U) #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_INACTIVE_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_MASK (0x20000000U) #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_SHIFT (29U) #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_START_DPRAW_MASK) /*! @} */ /*! @name D_ADD7_ATT0 - DMSS ADD7 ATT0 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_MASK (0x10000U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_SHIFT (16U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_MOM_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_MASK (0xE0000U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_SHIFT (17U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_AP_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_MASK (0xF000000U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_SHIFT (24U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_RQOS_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_MASK (0xF0000000U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_SHIFT (28U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT0_WQOS_MASK) /*! @} */ /*! @name D_ADD7_ATT1 - DMSS ADD7 ATT1 */ /*! @{ */ #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_MASK (0x1U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_SHIFT (0U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_WIDTH (1U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_EXACT_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_MASK (0x1EU) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_SHIFT (1U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_WR_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_MASK (0x1E0U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_SHIFT (5U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_L2A_RD_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_MASK (0x1E00U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_SHIFT (9U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_DABSZ_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_MASK (0x1E000U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_SHIFT (13U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_WIDTH (4U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_DADOL_MASK) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_MASK (0x1C0000U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_SHIFT (18U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_WIDTH (3U) #define INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL(x) (((uint32_t)(((uint32_t)(x)) << INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_SHIFT)) & INTERFACE_CONFIGURATION_D_ADD7_ATT1_DAUOL_MASK) /*! @} */ /*! * @} */ /* end of group INTERFACE_CONFIGURATION_Register_Masks */ /*! * @} */ /* end of group INTERFACE_CONFIGURATION_Peripheral_Access_Layer */ #endif /* #if !defined(S32Z2_INTERFACE_CONFIGURATION_H_) */