| /hal_nxp-latest/mcux/mcux-sdk/drivers/lcdifv2/ |
| D | fsl_lcdifv2.h | 380 base->INT[domain].INT_ENABLE |= mask; in LCDIFV2_EnableInterrupts()
392 base->INT[domain].INT_ENABLE &= ~mask; in LCDIFV2_DisableInterrupts()
404 return base->INT[domain].INT_STATUS; in LCDIFV2_GetInterruptStatus()
416 base->INT[domain].INT_STATUS = mask; in LCDIFV2_ClearInterruptStatus()
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| D | fsl_lcdifv2.c | 82 base->INT[0].INT_ENABLE = 0U; in LCDIFV2_ResetRegister()
83 base->INT[1].INT_ENABLE = 0U; in LCDIFV2_ResetRegister()
103 base->INT[0].INT_STATUS = 0xFFFFFFFFU; in LCDIFV2_ResetRegister()
104 base->INT[1].INT_STATUS = 0xFFFFFFFFU; in LCDIFV2_ResetRegister()
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| /hal_nxp-latest/mcux/mcux-sdk/scripts/kconfig/ |
| D | guiconfig.py | 82 BOOL, TRISTATE, STRING, INT, HEX, \
828 elif sym.orig_type in (INT, HEX):
868 if item.orig_type in (STRING, INT, HEX):
1012 return sc.orig_type in (STRING, INT, HEX) or len(sc.assignable) > 1 \
1123 if sc.type in (INT, HEX, STRING):
1299 if sym.type not in (INT, HEX):
1303 base = 10 if sym.type == INT else 16
1337 if sym.type in (INT, HEX):
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| D | menuconfig.py | 219 BOOL, TRISTATE, STRING, INT, HEX, \
1580 if sc.orig_type in (INT, HEX, STRING):
1591 if sc.orig_type in (INT, HEX):
1640 return sc.orig_type in (STRING, INT, HEX) or len(sc.assignable) > 1 \
3048 if item.orig_type in (STRING, INT, HEX):
3082 if sym.orig_type not in (INT, HEX):
3085 base = 10 if sym.orig_type == INT else 16
3112 if sym.orig_type in (INT, HEX):
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| D | kconfiglib.py | 4392 if self.orig_type is INT else \
4617 self.orig_type is INT and _is_base_n(value, 10) or
6986 INT = _T_INT variable
6994 INT: "int",
7002 INT: 10,
7011 _T_DEF_INT: INT,
7081 INT,
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_EDMA4_MP.h | 78 …__I uint32_t INT; /**< Management Page Interrupt Request Status Reg… member
|
| D | S32Z2_FEED_DMA_MP.h | 78 …__I uint32_t INT; /**< Management Page Interrupt Request Status, of… member
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| D | S32Z2_EDMA3_MP.h | 78 …__I uint32_t INT; /**< Management Page Interrupt Request Status, of… member
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| D | S32Z2_RESULT_DMA_MP.h | 78 …__I uint32_t INT; /**< Management Page Interrupt Request Status, of… member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_DMA.h | 78 …__I uint32_t INT; /**< Management Page Interrupt Request Status, of… member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/pdb/ |
| D | fsl_pdb.h | 563 base->DAC[channel].INT = PDB_INT_INT(value); in PDB_SetDACTriggerIntervalValue()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/ |
| D | fsl_edma.c | 176 EDMA_BASE(base)->INT = 0xFFFFFFFFU; in EDMA_Init()
2522 if ((handle->base->INT >> channel) != 0U) in EDMA_HandleIRQ()
2643 if ((s_edmaBases[instance]->INT >> channel) != 0U) in EDMA_DriverIRQHandler()
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| D | fsl_edma_core.h | 97 #define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U))
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/ |
| D | fsl_edma.c | 176 EDMA_BASE(base)->INT = 0xFFFFFFFFU; in EDMA_Init()
2522 if ((handle->base->INT >> channel) != 0U) in EDMA_HandleIRQ()
2643 if ((s_edmaBases[instance]->INT >> channel) != 0U) in EDMA_DriverIRQHandler()
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| D | fsl_edma_core.h | 97 #define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U))
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K118_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K116_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K142W_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K144W_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K142_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K144_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K148_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
|
| D | S32K146_DMA.h | 92 __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma/ |
| D | fsl_edma.c | 133 base->INT = 0xFFFFFFFFU; in EDMA_Init()
778 retval |= ((((uint32_t)base->INT >> channel) & 0x1U) << 2U); in EDMA_GetChannelStatusFlags()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/ |
| D | MK02F12810.h | 1562 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ member
7072 …__IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154… member
|
