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Searched refs:INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h34886 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
34891 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h34856 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
34861 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h45021 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45026 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
DMCXN546_cm33_core1.h45021 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45026 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h45021 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45026 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
DMCXN547_cm33_core1.h45021 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45026 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h45448 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45453 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
DMCXN947_cm33_core0.h45448 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45453 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h45448 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45453 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…
DMCXN946_cm33_core1.h45448 #define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) macro
45453 …_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)…