Searched refs:INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (Results 1 – 10 of 10) sorted by relevance
31444 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) macro31450 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK)
31414 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) macro31420 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK)
41021 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) macro41027 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK)
41448 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) macro41454 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK)
