Searched refs:INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (Results 1 – 10 of 10) sorted by relevance
31380 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) macro31386 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK)
31350 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) macro31356 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK)
40957 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) macro40963 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK)
41384 #define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) macro41390 …2_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK)
