| /hal_nxp-latest/mcux/mcux-sdk/drivers/gpc_1/ |
| D | fsl_gpc.c | 37 base->IMR[irqRegNum] &= ~(1UL << irqRegShiftNum); in GPC_EnableIRQ()
41 base->IMR[irqRegNum - 1UL] &= ~(1UL << irqRegShiftNum); in GPC_EnableIRQ()
65 base->IMR[irqRegNum] |= (1UL << irqRegShiftNum); in GPC_DisableIRQ()
69 base->IMR[irqRegNum - 1UL] |= (1UL << irqRegShiftNum); in GPC_DisableIRQ()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/igpio/ |
| D | fsl_gpio.h | 255 base->IMR |= mask; in GPIO_PortEnableInterrupts()
277 base->IMR &= ~mask; in GPIO_PortDisableInterrupts()
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| D | fsl_gpio.c | 89 base->IMR &= ~(1UL << pin); in GPIO_PinInit()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lcdic/ |
| D | fsl_lcdic.h | 468 base->IMR &= ~interrupts; in LCDIC_EnableInterrupts()
479 base->IMR |= interrupts; in LCDIC_DisableInterrupts()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/cns_dac/ |
| D | fsl_dac.h | 613 base->IMR &= ~interruptMask; in DAC_EnableInterrupts()
624 base->IMR |= interruptMask; in DAC_DisableInterrupts()
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/src/ |
| D | Adc_Sar_Ip.c | 1587 IMRAddr = &(AdcAEBasePtr->IMR); in Adc_CheckAndCallAllChannelNotification()
1599 IMRAddr = &(AdcBasePtr->IMR); in Adc_CheckAndCallAllChannelNotification()
1795 Imr = AdcAEBasePtr->IMR; in Adc_Sar_Ip_IRQHandler()
1807 Imr = AdcBasePtr->IMR; in Adc_Sar_Ip_IRQHandler()
3580 AdcAEBasePtr->IMR |= ImrFlags; in Adc_Sar_Ip_EnableNotifications()
3588 AdcBasePtr->IMR |= ImrFlags; in Adc_Sar_Ip_EnableNotifications()
3642 AdcAEBasePtr->IMR &= ~(ImrFlags); in Adc_Sar_Ip_DisableNotifications()
3650 AdcBasePtr->IMR &= ~(ImrFlags); in Adc_Sar_Ip_DisableNotifications()
5071 const uint32 Imr = AdcBasePtr->IMR; in Adc_Sar_Ip_TempSenseGetTemp()
5082 AdcBasePtr->IMR = 0UL; in Adc_Sar_Ip_TempSenseGetTemp()
[all …]
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/src/ |
| D | Adc_Sar_Ip.c | 1476 Imr = AdcAEBasePtr->IMR; in Adc_Sar_CheckAndCallEoctuNotification()
1485 Imr = AdcBasePtr->IMR; in Adc_Sar_CheckAndCallEoctuNotification()
1694 IMRAddr = (volatile uint32 *)&(AdcAEBasePtr->IMR); in Adc_CheckAndCallAllChannelNotification()
1706 IMRAddr = (volatile uint32 *)&(AdcBasePtr->IMR); in Adc_CheckAndCallAllChannelNotification()
1907 Imr = AdcAEBasePtr->IMR; in Adc_Sar_Ip_IRQHandler()
1919 Imr = AdcBasePtr->IMR; in Adc_Sar_Ip_IRQHandler()
3808 AdcAEBasePtr->IMR |= ImrFlags; in Adc_Sar_Ip_EnableNotifications()
3816 AdcBasePtr->IMR |= ImrFlags; in Adc_Sar_Ip_EnableNotifications()
3870 AdcAEBasePtr->IMR &= ~(ImrFlags); in Adc_Sar_Ip_DisableNotifications()
3878 AdcBasePtr->IMR &= ~(ImrFlags); in Adc_Sar_Ip_DisableNotifications()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/eqdc/ |
| D | fsl_eqdc.h | 734 return base->IMR; in EQDC_GetSignalStatusFlags()
745 …return ((0U != (base->IMR & EQDC_IMR_DIR_MASK)) ? kEQDC_CountDirectionUp : kEQDC_CountDirectionDow… in EQDC_GetLastCountDirection()
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| D | fsl_eqdc.c | 124 base->IMR = EQDC_IMR_FPHA(psConfig->filterPhaseA) | EQDC_IMR_FPHB(psConfig->filterPhaseB) | in EQDC_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qdc/ |
| D | fsl_qdc.h | 395 return base->IMR; in QDC_GetSignalStatusFlags()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/enc/ |
| D | fsl_enc.h | 396 return base->IMR; in ENC_GetSignalStatusFlags()
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_ADC.h | 84 __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x20 */ member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_ADC.h | 89 __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x20 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 14448 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
16895 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
17040 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 16008 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
20234 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
20379 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 15988 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
20214 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
20359 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 18101 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
22358 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
22503 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 17035 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
21171 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
21316 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 18103 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
22360 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
22505 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 17820 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
21956 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
22101 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 18469 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
22736 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
22881 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 19255 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
23522 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
23667 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 19333 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
23593 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
23738 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/ |
| D | LPC55S36.h | 12259 __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ member
35786 __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ member
49538 __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0x8 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 14401 …__IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register… member
14546 …__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ member
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