1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_I3C.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_I3C 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_I3C_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_I3C_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- I3C Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer 68 * @{ 69 */ 70 71 /** I3C - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ 74 __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ 75 __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ 76 uint8_t RESERVED_0[4]; 77 __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ 78 __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ 79 __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ 80 __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ 81 __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ 82 uint8_t RESERVED_1[8]; 83 __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ 84 __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ 85 __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ 86 __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ 87 __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ 88 __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ 89 uint8_t RESERVED_2[4]; 90 union { /* offset: 0x48 */ 91 __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0x48 */ 92 __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ 93 } SRDATAH_MRDATAH; 94 uint8_t RESERVED_3[8]; 95 union { /* offset: 0x54 */ 96 __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ 97 } SWDATA_B_H; 98 uint8_t RESERVED_4[4]; 99 __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ 100 __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ 101 uint8_t RESERVED_5[12]; 102 uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ 103 uint8_t RESERVED_6[8]; 104 __I uint32_t SMSGLAST; /**< Target Message Last Matched, offset: 0x7C */ 105 uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ 106 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ 107 __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ 108 uint8_t RESERVED_7[4]; 109 __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ 110 __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ 111 __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ 112 __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ 113 __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ 114 uint8_t RESERVED_8[8]; 115 __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ 116 __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ 117 __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ 118 __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ 119 __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ 120 __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ 121 uint8_t RESERVED_9[8]; 122 union { /* offset: 0xCC */ 123 __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ 124 } MWDATA_B1_H1; 125 union { /* offset: 0xD0 */ 126 __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ 127 __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ 128 } MWMSG_SDR; 129 __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ 130 uint8_t RESERVED_10[72]; 131 __IO uint32_t SMAPCTRL1; /**< Map Feature Control 1, offset: 0x120 */ 132 uint8_t RESERVED_11[3788]; 133 __IO uint32_t SELFRESET; /**< Self Reset, offset: 0xFF0 */ 134 } I3C_Type, *I3C_MemMapPtr; 135 136 /** Number of instances of the I3C module. */ 137 #define I3C_INSTANCE_COUNT (1u) 138 139 /* I3C - Peripheral instance base addresses */ 140 /** Peripheral I3C_0 base address */ 141 #define IP_I3C_0_BASE (0x401D0000u) 142 /** Peripheral I3C_0 base pointer */ 143 #define IP_I3C_0 ((I3C_Type *)IP_I3C_0_BASE) 144 /** Array initializer of I3C peripheral base addresses */ 145 #define IP_I3C_BASE_ADDRS { IP_I3C_0_BASE } 146 /** Array initializer of I3C peripheral base pointers */ 147 #define IP_I3C_BASE_PTRS { IP_I3C_0 } 148 149 /* ---------------------------------------------------------------------------- 150 -- I3C Register Masks 151 ---------------------------------------------------------------------------- */ 152 153 /*! 154 * @addtogroup I3C_Register_Masks I3C Register Masks 155 * @{ 156 */ 157 158 /*! @name MCONFIG - Controller Configuration */ 159 /*! @{ */ 160 161 #define I3C_MCONFIG_MSTENA_MASK (0x3U) 162 #define I3C_MCONFIG_MSTENA_SHIFT (0U) 163 #define I3C_MCONFIG_MSTENA_WIDTH (2U) 164 #define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) 165 166 #define I3C_MCONFIG_DISTO_MASK (0x8U) 167 #define I3C_MCONFIG_DISTO_SHIFT (3U) 168 #define I3C_MCONFIG_DISTO_WIDTH (1U) 169 #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) 170 171 #define I3C_MCONFIG_HKEEP_MASK (0x30U) 172 #define I3C_MCONFIG_HKEEP_SHIFT (4U) 173 #define I3C_MCONFIG_HKEEP_WIDTH (2U) 174 #define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) 175 176 #define I3C_MCONFIG_PPBAUD_MASK (0xF00U) 177 #define I3C_MCONFIG_PPBAUD_SHIFT (8U) 178 #define I3C_MCONFIG_PPBAUD_WIDTH (4U) 179 #define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) 180 181 #define I3C_MCONFIG_PPLOW_MASK (0xF000U) 182 #define I3C_MCONFIG_PPLOW_SHIFT (12U) 183 #define I3C_MCONFIG_PPLOW_WIDTH (4U) 184 #define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) 185 186 #define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) 187 #define I3C_MCONFIG_ODBAUD_SHIFT (16U) 188 #define I3C_MCONFIG_ODBAUD_WIDTH (8U) 189 #define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) 190 191 #define I3C_MCONFIG_SKEW_MASK (0xE000000U) 192 #define I3C_MCONFIG_SKEW_SHIFT (25U) 193 #define I3C_MCONFIG_SKEW_WIDTH (3U) 194 #define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) 195 196 #define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) 197 #define I3C_MCONFIG_I2CBAUD_SHIFT (28U) 198 #define I3C_MCONFIG_I2CBAUD_WIDTH (4U) 199 #define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) 200 /*! @} */ 201 202 /*! @name SCONFIG - Target Configuration */ 203 /*! @{ */ 204 205 #define I3C_SCONFIG_SLVENA_MASK (0x1U) 206 #define I3C_SCONFIG_SLVENA_SHIFT (0U) 207 #define I3C_SCONFIG_SLVENA_WIDTH (1U) 208 #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) 209 210 #define I3C_SCONFIG_NACK_MASK (0x2U) 211 #define I3C_SCONFIG_NACK_SHIFT (1U) 212 #define I3C_SCONFIG_NACK_WIDTH (1U) 213 #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) 214 215 #define I3C_SCONFIG_MATCHSS_MASK (0x4U) 216 #define I3C_SCONFIG_MATCHSS_SHIFT (2U) 217 #define I3C_SCONFIG_MATCHSS_WIDTH (1U) 218 #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) 219 220 #define I3C_SCONFIG_BAMATCH_MASK (0x3F0000U) 221 #define I3C_SCONFIG_BAMATCH_SHIFT (16U) 222 #define I3C_SCONFIG_BAMATCH_WIDTH (6U) 223 #define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) 224 225 #define I3C_SCONFIG_SADDR_MASK (0xFE000000U) 226 #define I3C_SCONFIG_SADDR_SHIFT (25U) 227 #define I3C_SCONFIG_SADDR_WIDTH (7U) 228 #define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) 229 /*! @} */ 230 231 /*! @name SSTATUS - Target Status */ 232 /*! @{ */ 233 234 #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) 235 #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) 236 #define I3C_SSTATUS_STNOTSTOP_WIDTH (1U) 237 #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) 238 239 #define I3C_SSTATUS_STMSG_MASK (0x2U) 240 #define I3C_SSTATUS_STMSG_SHIFT (1U) 241 #define I3C_SSTATUS_STMSG_WIDTH (1U) 242 #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) 243 244 #define I3C_SSTATUS_STREQRD_MASK (0x8U) 245 #define I3C_SSTATUS_STREQRD_SHIFT (3U) 246 #define I3C_SSTATUS_STREQRD_WIDTH (1U) 247 #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) 248 249 #define I3C_SSTATUS_STREQWR_MASK (0x10U) 250 #define I3C_SSTATUS_STREQWR_SHIFT (4U) 251 #define I3C_SSTATUS_STREQWR_WIDTH (1U) 252 #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) 253 254 #define I3C_SSTATUS_START_MASK (0x100U) 255 #define I3C_SSTATUS_START_SHIFT (8U) 256 #define I3C_SSTATUS_START_WIDTH (1U) 257 #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) 258 259 #define I3C_SSTATUS_MATCHED_MASK (0x200U) 260 #define I3C_SSTATUS_MATCHED_SHIFT (9U) 261 #define I3C_SSTATUS_MATCHED_WIDTH (1U) 262 #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) 263 264 #define I3C_SSTATUS_STOP_MASK (0x400U) 265 #define I3C_SSTATUS_STOP_SHIFT (10U) 266 #define I3C_SSTATUS_STOP_WIDTH (1U) 267 #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) 268 269 #define I3C_SSTATUS_RX_PEND_MASK (0x800U) 270 #define I3C_SSTATUS_RX_PEND_SHIFT (11U) 271 #define I3C_SSTATUS_RX_PEND_WIDTH (1U) 272 #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) 273 274 #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) 275 #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) 276 #define I3C_SSTATUS_TXNOTFULL_WIDTH (1U) 277 #define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) 278 279 #define I3C_SSTATUS_ERRWARN_MASK (0x8000U) 280 #define I3C_SSTATUS_ERRWARN_SHIFT (15U) 281 #define I3C_SSTATUS_ERRWARN_WIDTH (1U) 282 #define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) 283 /*! @} */ 284 285 /*! @name SINTSET - Target Interrupt Set */ 286 /*! @{ */ 287 288 #define I3C_SINTSET_START_MASK (0x100U) 289 #define I3C_SINTSET_START_SHIFT (8U) 290 #define I3C_SINTSET_START_WIDTH (1U) 291 #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) 292 293 #define I3C_SINTSET_MATCHED_MASK (0x200U) 294 #define I3C_SINTSET_MATCHED_SHIFT (9U) 295 #define I3C_SINTSET_MATCHED_WIDTH (1U) 296 #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) 297 298 #define I3C_SINTSET_STOP_MASK (0x400U) 299 #define I3C_SINTSET_STOP_SHIFT (10U) 300 #define I3C_SINTSET_STOP_WIDTH (1U) 301 #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) 302 303 #define I3C_SINTSET_RXPEND_MASK (0x800U) 304 #define I3C_SINTSET_RXPEND_SHIFT (11U) 305 #define I3C_SINTSET_RXPEND_WIDTH (1U) 306 #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) 307 308 #define I3C_SINTSET_TXSEND_MASK (0x1000U) 309 #define I3C_SINTSET_TXSEND_SHIFT (12U) 310 #define I3C_SINTSET_TXSEND_WIDTH (1U) 311 #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) 312 313 #define I3C_SINTSET_ERRWARN_MASK (0x8000U) 314 #define I3C_SINTSET_ERRWARN_SHIFT (15U) 315 #define I3C_SINTSET_ERRWARN_WIDTH (1U) 316 #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) 317 /*! @} */ 318 319 /*! @name SINTCLR - Target Interrupt Clear */ 320 /*! @{ */ 321 322 #define I3C_SINTCLR_START_MASK (0x100U) 323 #define I3C_SINTCLR_START_SHIFT (8U) 324 #define I3C_SINTCLR_START_WIDTH (1U) 325 #define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) 326 327 #define I3C_SINTCLR_MATCHED_MASK (0x200U) 328 #define I3C_SINTCLR_MATCHED_SHIFT (9U) 329 #define I3C_SINTCLR_MATCHED_WIDTH (1U) 330 #define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) 331 332 #define I3C_SINTCLR_STOP_MASK (0x400U) 333 #define I3C_SINTCLR_STOP_SHIFT (10U) 334 #define I3C_SINTCLR_STOP_WIDTH (1U) 335 #define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) 336 337 #define I3C_SINTCLR_RXPEND_MASK (0x800U) 338 #define I3C_SINTCLR_RXPEND_SHIFT (11U) 339 #define I3C_SINTCLR_RXPEND_WIDTH (1U) 340 #define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) 341 342 #define I3C_SINTCLR_TXSEND_MASK (0x1000U) 343 #define I3C_SINTCLR_TXSEND_SHIFT (12U) 344 #define I3C_SINTCLR_TXSEND_WIDTH (1U) 345 #define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) 346 347 #define I3C_SINTCLR_ERRWARN_MASK (0x8000U) 348 #define I3C_SINTCLR_ERRWARN_SHIFT (15U) 349 #define I3C_SINTCLR_ERRWARN_WIDTH (1U) 350 #define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) 351 /*! @} */ 352 353 /*! @name SINTMASKED - Target Interrupt Mask */ 354 /*! @{ */ 355 356 #define I3C_SINTMASKED_START_MASK (0x100U) 357 #define I3C_SINTMASKED_START_SHIFT (8U) 358 #define I3C_SINTMASKED_START_WIDTH (1U) 359 #define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) 360 361 #define I3C_SINTMASKED_MATCHED_MASK (0x200U) 362 #define I3C_SINTMASKED_MATCHED_SHIFT (9U) 363 #define I3C_SINTMASKED_MATCHED_WIDTH (1U) 364 #define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) 365 366 #define I3C_SINTMASKED_STOP_MASK (0x400U) 367 #define I3C_SINTMASKED_STOP_SHIFT (10U) 368 #define I3C_SINTMASKED_STOP_WIDTH (1U) 369 #define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) 370 371 #define I3C_SINTMASKED_RXPEND_MASK (0x800U) 372 #define I3C_SINTMASKED_RXPEND_SHIFT (11U) 373 #define I3C_SINTMASKED_RXPEND_WIDTH (1U) 374 #define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) 375 376 #define I3C_SINTMASKED_TXSEND_MASK (0x1000U) 377 #define I3C_SINTMASKED_TXSEND_SHIFT (12U) 378 #define I3C_SINTMASKED_TXSEND_WIDTH (1U) 379 #define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) 380 381 #define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) 382 #define I3C_SINTMASKED_ERRWARN_SHIFT (15U) 383 #define I3C_SINTMASKED_ERRWARN_WIDTH (1U) 384 #define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) 385 /*! @} */ 386 387 /*! @name SERRWARN - Target Errors and Warnings */ 388 /*! @{ */ 389 390 #define I3C_SERRWARN_ORUN_MASK (0x1U) 391 #define I3C_SERRWARN_ORUN_SHIFT (0U) 392 #define I3C_SERRWARN_ORUN_WIDTH (1U) 393 #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) 394 395 #define I3C_SERRWARN_URUN_MASK (0x2U) 396 #define I3C_SERRWARN_URUN_SHIFT (1U) 397 #define I3C_SERRWARN_URUN_WIDTH (1U) 398 #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) 399 400 #define I3C_SERRWARN_URUNNACK_MASK (0x4U) 401 #define I3C_SERRWARN_URUNNACK_SHIFT (2U) 402 #define I3C_SERRWARN_URUNNACK_WIDTH (1U) 403 #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) 404 405 #define I3C_SERRWARN_TERM_MASK (0x8U) 406 #define I3C_SERRWARN_TERM_SHIFT (3U) 407 #define I3C_SERRWARN_TERM_WIDTH (1U) 408 #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) 409 410 #define I3C_SERRWARN_INVSTART_MASK (0x10U) 411 #define I3C_SERRWARN_INVSTART_SHIFT (4U) 412 #define I3C_SERRWARN_INVSTART_WIDTH (1U) 413 #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) 414 415 #define I3C_SERRWARN_SPAR_MASK (0x100U) 416 #define I3C_SERRWARN_SPAR_SHIFT (8U) 417 #define I3C_SERRWARN_SPAR_WIDTH (1U) 418 #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) 419 420 #define I3C_SERRWARN_OREAD_MASK (0x10000U) 421 #define I3C_SERRWARN_OREAD_SHIFT (16U) 422 #define I3C_SERRWARN_OREAD_WIDTH (1U) 423 #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) 424 425 #define I3C_SERRWARN_OWRITE_MASK (0x20000U) 426 #define I3C_SERRWARN_OWRITE_SHIFT (17U) 427 #define I3C_SERRWARN_OWRITE_WIDTH (1U) 428 #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) 429 /*! @} */ 430 431 /*! @name SDMACTRL - Target DMA Control */ 432 /*! @{ */ 433 434 #define I3C_SDMACTRL_DMAFB_MASK (0x3U) 435 #define I3C_SDMACTRL_DMAFB_SHIFT (0U) 436 #define I3C_SDMACTRL_DMAFB_WIDTH (2U) 437 #define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) 438 439 #define I3C_SDMACTRL_DMATB_MASK (0xCU) 440 #define I3C_SDMACTRL_DMATB_SHIFT (2U) 441 #define I3C_SDMACTRL_DMATB_WIDTH (2U) 442 #define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) 443 444 #define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) 445 #define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) 446 #define I3C_SDMACTRL_DMAWIDTH_WIDTH (2U) 447 #define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) 448 /*! @} */ 449 450 /*! @name SDATACTRL - Target Data Control */ 451 /*! @{ */ 452 453 #define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) 454 #define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) 455 #define I3C_SDATACTRL_FLUSHTB_WIDTH (1U) 456 #define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) 457 458 #define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) 459 #define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) 460 #define I3C_SDATACTRL_FLUSHFB_WIDTH (1U) 461 #define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) 462 463 #define I3C_SDATACTRL_UNLOCK_MASK (0x8U) 464 #define I3C_SDATACTRL_UNLOCK_SHIFT (3U) 465 #define I3C_SDATACTRL_UNLOCK_WIDTH (1U) 466 #define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) 467 468 #define I3C_SDATACTRL_TXTRIG_MASK (0x30U) 469 #define I3C_SDATACTRL_TXTRIG_SHIFT (4U) 470 #define I3C_SDATACTRL_TXTRIG_WIDTH (2U) 471 #define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) 472 473 #define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) 474 #define I3C_SDATACTRL_RXTRIG_SHIFT (6U) 475 #define I3C_SDATACTRL_RXTRIG_WIDTH (2U) 476 #define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) 477 478 #define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) 479 #define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) 480 #define I3C_SDATACTRL_TXCOUNT_WIDTH (5U) 481 #define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) 482 483 #define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) 484 #define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) 485 #define I3C_SDATACTRL_RXCOUNT_WIDTH (5U) 486 #define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) 487 488 #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) 489 #define I3C_SDATACTRL_TXFULL_SHIFT (30U) 490 #define I3C_SDATACTRL_TXFULL_WIDTH (1U) 491 #define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) 492 493 #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) 494 #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) 495 #define I3C_SDATACTRL_RXEMPTY_WIDTH (1U) 496 #define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) 497 /*! @} */ 498 499 /*! @name SWDATAB - Target Write Data Byte */ 500 /*! @{ */ 501 502 #define I3C_SWDATAB_DATA_MASK (0xFFU) 503 #define I3C_SWDATAB_DATA_SHIFT (0U) 504 #define I3C_SWDATAB_DATA_WIDTH (8U) 505 #define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) 506 507 #define I3C_SWDATAB_END_MASK (0x100U) 508 #define I3C_SWDATAB_END_SHIFT (8U) 509 #define I3C_SWDATAB_END_WIDTH (1U) 510 #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) 511 512 #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) 513 #define I3C_SWDATAB_END_ALSO_SHIFT (16U) 514 #define I3C_SWDATAB_END_ALSO_WIDTH (1U) 515 #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) 516 /*! @} */ 517 518 /*! @name SWDATABE - Target Write Data Byte End */ 519 /*! @{ */ 520 521 #define I3C_SWDATABE_DATA_MASK (0xFFU) 522 #define I3C_SWDATABE_DATA_SHIFT (0U) 523 #define I3C_SWDATABE_DATA_WIDTH (8U) 524 #define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) 525 /*! @} */ 526 527 /*! @name SWDATAH - Target Write Data Halfword */ 528 /*! @{ */ 529 530 #define I3C_SWDATAH_DATA0_MASK (0xFFU) 531 #define I3C_SWDATAH_DATA0_SHIFT (0U) 532 #define I3C_SWDATAH_DATA0_WIDTH (8U) 533 #define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) 534 535 #define I3C_SWDATAH_DATA1_MASK (0xFF00U) 536 #define I3C_SWDATAH_DATA1_SHIFT (8U) 537 #define I3C_SWDATAH_DATA1_WIDTH (8U) 538 #define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) 539 540 #define I3C_SWDATAH_END_MASK (0x10000U) 541 #define I3C_SWDATAH_END_SHIFT (16U) 542 #define I3C_SWDATAH_END_WIDTH (1U) 543 #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) 544 /*! @} */ 545 546 /*! @name SWDATAHE - Target Write Data Halfword End */ 547 /*! @{ */ 548 549 #define I3C_SWDATAHE_DATA0_MASK (0xFFU) 550 #define I3C_SWDATAHE_DATA0_SHIFT (0U) 551 #define I3C_SWDATAHE_DATA0_WIDTH (8U) 552 #define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) 553 554 #define I3C_SWDATAHE_DATA1_MASK (0xFF00U) 555 #define I3C_SWDATAHE_DATA1_SHIFT (8U) 556 #define I3C_SWDATAHE_DATA1_WIDTH (8U) 557 #define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) 558 /*! @} */ 559 560 /*! @name SRDATAB - Target Read Data Byte */ 561 /*! @{ */ 562 563 #define I3C_SRDATAB_DATA0_MASK (0xFFU) 564 #define I3C_SRDATAB_DATA0_SHIFT (0U) 565 #define I3C_SRDATAB_DATA0_WIDTH (8U) 566 #define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) 567 /*! @} */ 568 569 /*! @name MRDATAH - Controller Read Data Halfword */ 570 /*! @{ */ 571 572 #define I3C_MRDATAH_LSB_MASK (0xFFU) 573 #define I3C_MRDATAH_LSB_SHIFT (0U) 574 #define I3C_MRDATAH_LSB_WIDTH (8U) 575 #define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) 576 577 #define I3C_MRDATAH_MSB_MASK (0xFF00U) 578 #define I3C_MRDATAH_MSB_SHIFT (8U) 579 #define I3C_MRDATAH_MSB_WIDTH (8U) 580 #define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) 581 /*! @} */ 582 583 /*! @name SRDATAH - Target Read Data Halfword */ 584 /*! @{ */ 585 586 #define I3C_SRDATAH_LSB_MASK (0xFFU) 587 #define I3C_SRDATAH_LSB_SHIFT (0U) 588 #define I3C_SRDATAH_LSB_WIDTH (8U) 589 #define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) 590 591 #define I3C_SRDATAH_MSB_MASK (0xFF00U) 592 #define I3C_SRDATAH_MSB_SHIFT (8U) 593 #define I3C_SRDATAH_MSB_WIDTH (8U) 594 #define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) 595 /*! @} */ 596 597 /*! @name SWDATAB1 - Target Write Data Byte */ 598 /*! @{ */ 599 600 #define I3C_SWDATAB1_DATA_MASK (0xFFU) 601 #define I3C_SWDATAB1_DATA_SHIFT (0U) 602 #define I3C_SWDATAB1_DATA_WIDTH (8U) 603 #define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) 604 /*! @} */ 605 606 /*! @name SCAPABILITIES2 - Target Capabilities 2 */ 607 /*! @{ */ 608 609 #define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) 610 #define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) 611 #define I3C_SCAPABILITIES2_I2C10B_WIDTH (1U) 612 #define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) 613 614 #define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) 615 #define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) 616 #define I3C_SCAPABILITIES2_I2CRST_WIDTH (1U) 617 #define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) 618 619 #define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) 620 #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) 621 #define I3C_SCAPABILITIES2_I2CDEVID_WIDTH (1U) 622 #define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) 623 /*! @} */ 624 625 /*! @name SCAPABILITIES - Target Capabilities */ 626 /*! @{ */ 627 628 #define I3C_SCAPABILITIES_MASTER_MASK (0x200U) 629 #define I3C_SCAPABILITIES_MASTER_SHIFT (9U) 630 #define I3C_SCAPABILITIES_MASTER_WIDTH (1U) 631 #define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) 632 633 #define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) 634 #define I3C_SCAPABILITIES_SADDR_SHIFT (10U) 635 #define I3C_SCAPABILITIES_SADDR_WIDTH (2U) 636 #define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) 637 638 #define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) 639 #define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) 640 #define I3C_SCAPABILITIES_EXTFIFO_WIDTH (3U) 641 #define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) 642 643 #define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) 644 #define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) 645 #define I3C_SCAPABILITIES_FIFOTX_WIDTH (2U) 646 #define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) 647 648 #define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) 649 #define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) 650 #define I3C_SCAPABILITIES_FIFORX_WIDTH (2U) 651 #define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) 652 653 #define I3C_SCAPABILITIES_INT_MASK (0x40000000U) 654 #define I3C_SCAPABILITIES_INT_SHIFT (30U) 655 #define I3C_SCAPABILITIES_INT_WIDTH (1U) 656 #define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) 657 658 #define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) 659 #define I3C_SCAPABILITIES_DMA_SHIFT (31U) 660 #define I3C_SCAPABILITIES_DMA_WIDTH (1U) 661 #define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) 662 /*! @} */ 663 664 /*! @name SMSGLAST - Target Message Last Matched */ 665 /*! @{ */ 666 667 #define I3C_SMSGLAST_LASTSTATIC_MASK (0x10U) 668 #define I3C_SMSGLAST_LASTSTATIC_SHIFT (4U) 669 #define I3C_SMSGLAST_LASTSTATIC_WIDTH (1U) 670 #define I3C_SMSGLAST_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGLAST_LASTSTATIC_SHIFT)) & I3C_SMSGLAST_LASTSTATIC_MASK) 671 /*! @} */ 672 673 /*! @name MCTRL - Controller Control */ 674 /*! @{ */ 675 676 #define I3C_MCTRL_REQUEST_MASK (0x7U) 677 #define I3C_MCTRL_REQUEST_SHIFT (0U) 678 #define I3C_MCTRL_REQUEST_WIDTH (3U) 679 #define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) 680 681 #define I3C_MCTRL_TYPE_MASK (0x30U) 682 #define I3C_MCTRL_TYPE_SHIFT (4U) 683 #define I3C_MCTRL_TYPE_WIDTH (2U) 684 #define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) 685 686 #define I3C_MCTRL_DIR_MASK (0x100U) 687 #define I3C_MCTRL_DIR_SHIFT (8U) 688 #define I3C_MCTRL_DIR_WIDTH (1U) 689 #define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) 690 691 #define I3C_MCTRL_ADDR_MASK (0xFE00U) 692 #define I3C_MCTRL_ADDR_SHIFT (9U) 693 #define I3C_MCTRL_ADDR_WIDTH (7U) 694 #define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) 695 696 #define I3C_MCTRL_RDTERM_MASK (0xFF0000U) 697 #define I3C_MCTRL_RDTERM_SHIFT (16U) 698 #define I3C_MCTRL_RDTERM_WIDTH (8U) 699 #define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) 700 /*! @} */ 701 702 /*! @name MSTATUS - Controller Status */ 703 /*! @{ */ 704 705 #define I3C_MSTATUS_STATE_MASK (0x7U) 706 #define I3C_MSTATUS_STATE_SHIFT (0U) 707 #define I3C_MSTATUS_STATE_WIDTH (3U) 708 #define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) 709 710 #define I3C_MSTATUS_BETWEEN_MASK (0x10U) 711 #define I3C_MSTATUS_BETWEEN_SHIFT (4U) 712 #define I3C_MSTATUS_BETWEEN_WIDTH (1U) 713 #define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) 714 715 #define I3C_MSTATUS_NACKED_MASK (0x20U) 716 #define I3C_MSTATUS_NACKED_SHIFT (5U) 717 #define I3C_MSTATUS_NACKED_WIDTH (1U) 718 #define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) 719 720 #define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) 721 #define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) 722 #define I3C_MSTATUS_MCTRLDONE_WIDTH (1U) 723 #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) 724 725 #define I3C_MSTATUS_COMPLETE_MASK (0x400U) 726 #define I3C_MSTATUS_COMPLETE_SHIFT (10U) 727 #define I3C_MSTATUS_COMPLETE_WIDTH (1U) 728 #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) 729 730 #define I3C_MSTATUS_RXPEND_MASK (0x800U) 731 #define I3C_MSTATUS_RXPEND_SHIFT (11U) 732 #define I3C_MSTATUS_RXPEND_WIDTH (1U) 733 #define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) 734 735 #define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) 736 #define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) 737 #define I3C_MSTATUS_TXNOTFULL_WIDTH (1U) 738 #define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) 739 740 #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) 741 #define I3C_MSTATUS_ERRWARN_SHIFT (15U) 742 #define I3C_MSTATUS_ERRWARN_WIDTH (1U) 743 #define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) 744 /*! @} */ 745 746 /*! @name MINTSET - Controller Interrupt Set */ 747 /*! @{ */ 748 749 #define I3C_MINTSET_MCTRLDONE_MASK (0x200U) 750 #define I3C_MINTSET_MCTRLDONE_SHIFT (9U) 751 #define I3C_MINTSET_MCTRLDONE_WIDTH (1U) 752 #define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) 753 754 #define I3C_MINTSET_COMPLETE_MASK (0x400U) 755 #define I3C_MINTSET_COMPLETE_SHIFT (10U) 756 #define I3C_MINTSET_COMPLETE_WIDTH (1U) 757 #define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) 758 759 #define I3C_MINTSET_RXPEND_MASK (0x800U) 760 #define I3C_MINTSET_RXPEND_SHIFT (11U) 761 #define I3C_MINTSET_RXPEND_WIDTH (1U) 762 #define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) 763 764 #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) 765 #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) 766 #define I3C_MINTSET_TXNOTFULL_WIDTH (1U) 767 #define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) 768 769 #define I3C_MINTSET_ERRWARN_MASK (0x8000U) 770 #define I3C_MINTSET_ERRWARN_SHIFT (15U) 771 #define I3C_MINTSET_ERRWARN_WIDTH (1U) 772 #define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) 773 /*! @} */ 774 775 /*! @name MINTCLR - Controller Interrupt Clear */ 776 /*! @{ */ 777 778 #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) 779 #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) 780 #define I3C_MINTCLR_MCTRLDONE_WIDTH (1U) 781 #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) 782 783 #define I3C_MINTCLR_COMPLETE_MASK (0x400U) 784 #define I3C_MINTCLR_COMPLETE_SHIFT (10U) 785 #define I3C_MINTCLR_COMPLETE_WIDTH (1U) 786 #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) 787 788 #define I3C_MINTCLR_RXPEND_MASK (0x800U) 789 #define I3C_MINTCLR_RXPEND_SHIFT (11U) 790 #define I3C_MINTCLR_RXPEND_WIDTH (1U) 791 #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) 792 793 #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) 794 #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) 795 #define I3C_MINTCLR_TXNOTFULL_WIDTH (1U) 796 #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) 797 798 #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) 799 #define I3C_MINTCLR_ERRWARN_SHIFT (15U) 800 #define I3C_MINTCLR_ERRWARN_WIDTH (1U) 801 #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) 802 /*! @} */ 803 804 /*! @name MINTMASKED - Controller Interrupt Mask */ 805 /*! @{ */ 806 807 #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) 808 #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) 809 #define I3C_MINTMASKED_MCTRLDONE_WIDTH (1U) 810 #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) 811 812 #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) 813 #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) 814 #define I3C_MINTMASKED_COMPLETE_WIDTH (1U) 815 #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) 816 817 #define I3C_MINTMASKED_RXPEND_MASK (0x800U) 818 #define I3C_MINTMASKED_RXPEND_SHIFT (11U) 819 #define I3C_MINTMASKED_RXPEND_WIDTH (1U) 820 #define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) 821 822 #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) 823 #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) 824 #define I3C_MINTMASKED_TXNOTFULL_WIDTH (1U) 825 #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) 826 827 #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) 828 #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) 829 #define I3C_MINTMASKED_ERRWARN_WIDTH (1U) 830 #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) 831 /*! @} */ 832 833 /*! @name MERRWARN - Controller Errors and Warnings */ 834 /*! @{ */ 835 836 #define I3C_MERRWARN_NACK_MASK (0x4U) 837 #define I3C_MERRWARN_NACK_SHIFT (2U) 838 #define I3C_MERRWARN_NACK_WIDTH (1U) 839 #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) 840 841 #define I3C_MERRWARN_WRABT_MASK (0x8U) 842 #define I3C_MERRWARN_WRABT_SHIFT (3U) 843 #define I3C_MERRWARN_WRABT_WIDTH (1U) 844 #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) 845 846 #define I3C_MERRWARN_OREAD_MASK (0x10000U) 847 #define I3C_MERRWARN_OREAD_SHIFT (16U) 848 #define I3C_MERRWARN_OREAD_WIDTH (1U) 849 #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) 850 851 #define I3C_MERRWARN_OWRITE_MASK (0x20000U) 852 #define I3C_MERRWARN_OWRITE_SHIFT (17U) 853 #define I3C_MERRWARN_OWRITE_WIDTH (1U) 854 #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) 855 856 #define I3C_MERRWARN_MSGERR_MASK (0x40000U) 857 #define I3C_MERRWARN_MSGERR_SHIFT (18U) 858 #define I3C_MERRWARN_MSGERR_WIDTH (1U) 859 #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) 860 861 #define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) 862 #define I3C_MERRWARN_TIMEOUT_SHIFT (20U) 863 #define I3C_MERRWARN_TIMEOUT_WIDTH (1U) 864 #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) 865 /*! @} */ 866 867 /*! @name MDMACTRL - Controller DMA Control */ 868 /*! @{ */ 869 870 #define I3C_MDMACTRL_DMAFB_MASK (0x3U) 871 #define I3C_MDMACTRL_DMAFB_SHIFT (0U) 872 #define I3C_MDMACTRL_DMAFB_WIDTH (2U) 873 #define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) 874 875 #define I3C_MDMACTRL_DMATB_MASK (0xCU) 876 #define I3C_MDMACTRL_DMATB_SHIFT (2U) 877 #define I3C_MDMACTRL_DMATB_WIDTH (2U) 878 #define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) 879 880 #define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) 881 #define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) 882 #define I3C_MDMACTRL_DMAWIDTH_WIDTH (2U) 883 #define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) 884 /*! @} */ 885 886 /*! @name MDATACTRL - Controller Data Control */ 887 /*! @{ */ 888 889 #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) 890 #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) 891 #define I3C_MDATACTRL_FLUSHTB_WIDTH (1U) 892 #define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) 893 894 #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) 895 #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) 896 #define I3C_MDATACTRL_FLUSHFB_WIDTH (1U) 897 #define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) 898 899 #define I3C_MDATACTRL_UNLOCK_MASK (0x8U) 900 #define I3C_MDATACTRL_UNLOCK_SHIFT (3U) 901 #define I3C_MDATACTRL_UNLOCK_WIDTH (1U) 902 #define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) 903 904 #define I3C_MDATACTRL_TXTRIG_MASK (0x30U) 905 #define I3C_MDATACTRL_TXTRIG_SHIFT (4U) 906 #define I3C_MDATACTRL_TXTRIG_WIDTH (2U) 907 #define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) 908 909 #define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) 910 #define I3C_MDATACTRL_RXTRIG_SHIFT (6U) 911 #define I3C_MDATACTRL_RXTRIG_WIDTH (2U) 912 #define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) 913 914 #define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) 915 #define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) 916 #define I3C_MDATACTRL_TXCOUNT_WIDTH (5U) 917 #define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) 918 919 #define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) 920 #define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) 921 #define I3C_MDATACTRL_RXCOUNT_WIDTH (5U) 922 #define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) 923 924 #define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) 925 #define I3C_MDATACTRL_TXFULL_SHIFT (30U) 926 #define I3C_MDATACTRL_TXFULL_WIDTH (1U) 927 #define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) 928 929 #define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) 930 #define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) 931 #define I3C_MDATACTRL_RXEMPTY_WIDTH (1U) 932 #define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) 933 /*! @} */ 934 935 /*! @name MWDATAB - Controller Write Data Byte */ 936 /*! @{ */ 937 938 #define I3C_MWDATAB_VALUE_MASK (0xFFU) 939 #define I3C_MWDATAB_VALUE_SHIFT (0U) 940 #define I3C_MWDATAB_VALUE_WIDTH (8U) 941 #define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) 942 943 #define I3C_MWDATAB_END_MASK (0x100U) 944 #define I3C_MWDATAB_END_SHIFT (8U) 945 #define I3C_MWDATAB_END_WIDTH (1U) 946 #define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) 947 948 #define I3C_MWDATAB_END_ALSO_MASK (0x10000U) 949 #define I3C_MWDATAB_END_ALSO_SHIFT (16U) 950 #define I3C_MWDATAB_END_ALSO_WIDTH (1U) 951 #define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) 952 /*! @} */ 953 954 /*! @name MWDATABE - Controller Write Data Byte End */ 955 /*! @{ */ 956 957 #define I3C_MWDATABE_VALUE_MASK (0xFFU) 958 #define I3C_MWDATABE_VALUE_SHIFT (0U) 959 #define I3C_MWDATABE_VALUE_WIDTH (8U) 960 #define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) 961 /*! @} */ 962 963 /*! @name MWDATAH - Controller Write Data Halfword */ 964 /*! @{ */ 965 966 #define I3C_MWDATAH_DATA0_MASK (0xFFU) 967 #define I3C_MWDATAH_DATA0_SHIFT (0U) 968 #define I3C_MWDATAH_DATA0_WIDTH (8U) 969 #define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) 970 971 #define I3C_MWDATAH_DATA1_MASK (0xFF00U) 972 #define I3C_MWDATAH_DATA1_SHIFT (8U) 973 #define I3C_MWDATAH_DATA1_WIDTH (8U) 974 #define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) 975 976 #define I3C_MWDATAH_END_MASK (0x10000U) 977 #define I3C_MWDATAH_END_SHIFT (16U) 978 #define I3C_MWDATAH_END_WIDTH (1U) 979 #define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) 980 /*! @} */ 981 982 /*! @name MWDATAHE - Controller Write Data Halfword End */ 983 /*! @{ */ 984 985 #define I3C_MWDATAHE_DATA0_MASK (0xFFU) 986 #define I3C_MWDATAHE_DATA0_SHIFT (0U) 987 #define I3C_MWDATAHE_DATA0_WIDTH (8U) 988 #define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) 989 990 #define I3C_MWDATAHE_DATA1_MASK (0xFF00U) 991 #define I3C_MWDATAHE_DATA1_SHIFT (8U) 992 #define I3C_MWDATAHE_DATA1_WIDTH (8U) 993 #define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) 994 /*! @} */ 995 996 /*! @name MRDATAB - Controller Read Data Byte */ 997 /*! @{ */ 998 999 #define I3C_MRDATAB_VALUE_MASK (0xFFU) 1000 #define I3C_MRDATAB_VALUE_SHIFT (0U) 1001 #define I3C_MRDATAB_VALUE_WIDTH (8U) 1002 #define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) 1003 /*! @} */ 1004 1005 /*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ 1006 /*! @{ */ 1007 1008 #define I3C_MWDATAB1_VALUE_MASK (0xFFU) 1009 #define I3C_MWDATAB1_VALUE_SHIFT (0U) 1010 #define I3C_MWDATAB1_VALUE_WIDTH (8U) 1011 #define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) 1012 /*! @} */ 1013 1014 /*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ 1015 /*! @{ */ 1016 1017 #define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) 1018 #define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) 1019 #define I3C_MWMSG_SDR_CONTROL_DIR_WIDTH (1U) 1020 #define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) 1021 1022 #define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) 1023 #define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) 1024 #define I3C_MWMSG_SDR_CONTROL_ADDR_WIDTH (7U) 1025 #define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) 1026 1027 #define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) 1028 #define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) 1029 #define I3C_MWMSG_SDR_CONTROL_END_WIDTH (1U) 1030 #define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) 1031 1032 #define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) 1033 #define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) 1034 #define I3C_MWMSG_SDR_CONTROL_I2C_WIDTH (1U) 1035 #define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) 1036 1037 #define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) 1038 #define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) 1039 #define I3C_MWMSG_SDR_CONTROL_LEN_WIDTH (5U) 1040 #define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) 1041 /*! @} */ 1042 1043 /*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ 1044 /*! @{ */ 1045 1046 #define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) 1047 #define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) 1048 #define I3C_MWMSG_SDR_DATA_DATA16B_WIDTH (16U) 1049 #define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) 1050 /*! @} */ 1051 1052 /*! @name MRMSG_SDR - Controller Read Message in SDR mode */ 1053 /*! @{ */ 1054 1055 #define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) 1056 #define I3C_MRMSG_SDR_DATA_SHIFT (0U) 1057 #define I3C_MRMSG_SDR_DATA_WIDTH (16U) 1058 #define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) 1059 /*! @} */ 1060 1061 /*! @name SMAPCTRL1 - Map Feature Control 1 */ 1062 /*! @{ */ 1063 1064 #define I3C_SMAPCTRL1_ENA_MASK (0x1U) 1065 #define I3C_SMAPCTRL1_ENA_SHIFT (0U) 1066 #define I3C_SMAPCTRL1_ENA_WIDTH (1U) 1067 #define I3C_SMAPCTRL1_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ENA_SHIFT)) & I3C_SMAPCTRL1_ENA_MASK) 1068 1069 #define I3C_SMAPCTRL1_ADDR_MASK (0xFEU) 1070 #define I3C_SMAPCTRL1_ADDR_SHIFT (1U) 1071 #define I3C_SMAPCTRL1_ADDR_WIDTH (7U) 1072 #define I3C_SMAPCTRL1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ADDR_SHIFT)) & I3C_SMAPCTRL1_ADDR_MASK) 1073 1074 #define I3C_SMAPCTRL1_MAPSA_MASK (0x100U) 1075 #define I3C_SMAPCTRL1_MAPSA_SHIFT (8U) 1076 #define I3C_SMAPCTRL1_MAPSA_WIDTH (1U) 1077 #define I3C_SMAPCTRL1_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_MAPSA_SHIFT)) & I3C_SMAPCTRL1_MAPSA_MASK) 1078 1079 #define I3C_SMAPCTRL1_NACK_MASK (0x1000U) 1080 #define I3C_SMAPCTRL1_NACK_SHIFT (12U) 1081 #define I3C_SMAPCTRL1_NACK_WIDTH (1U) 1082 #define I3C_SMAPCTRL1_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_NACK_SHIFT)) & I3C_SMAPCTRL1_NACK_MASK) 1083 /*! @} */ 1084 1085 /*! @name SELFRESET - Self Reset */ 1086 /*! @{ */ 1087 1088 #define I3C_SELFRESET_RST_MASK (0x1U) 1089 #define I3C_SELFRESET_RST_SHIFT (0U) 1090 #define I3C_SELFRESET_RST_WIDTH (1U) 1091 #define I3C_SELFRESET_RST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_RST_SHIFT)) & I3C_SELFRESET_RST_MASK) 1092 1093 #define I3C_SELFRESET_KEY_MASK (0xFFFFFF00U) 1094 #define I3C_SELFRESET_KEY_SHIFT (8U) 1095 #define I3C_SELFRESET_KEY_WIDTH (24U) 1096 #define I3C_SELFRESET_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_KEY_SHIFT)) & I3C_SELFRESET_KEY_MASK) 1097 /*! @} */ 1098 1099 /*! 1100 * @} 1101 */ /* end of group I3C_Register_Masks */ 1102 1103 /*! 1104 * @} 1105 */ /* end of group I3C_Peripheral_Access_Layer */ 1106 1107 #endif /* #if !defined(S32Z2_I3C_H_) */ 1108
