/* * Copyright 1997-2016 Freescale Semiconductor, Inc. * Copyright 2016-2024 NXP * * SPDX-License-Identifier: BSD-3-Clause */ /*! * @file S32Z2_I3C.h * @version 2.3 * @date 2024-05-03 * @brief Peripheral Access Layer for S32Z2_I3C * * This file contains register definitions and macros for easy access to their * bit fields. * * This file assumes LITTLE endian system. */ /** * @page misra_violations MISRA-C:2012 violations * * @section [global] * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced * The SoC header defines typedef for all modules. * * @section [global] * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced * The SoC header defines macros for all modules and registers. * * @section [global] * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro * These are generated macros used for accessing the bit-fields from registers. * * @section [global] * Violates MISRA 2012 Required Rule 5.1, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.2, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.4, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 5.5, identifier clash * The supported compilers use more than 31 significant characters for identifiers. * * @section [global] * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler * This type qualifier is needed to ensure correct I/O access and addressing. */ /* Prevention from multiple including the same memory map */ #if !defined(S32Z2_I3C_H_) /* Check if memory map has not been already included */ #define S32Z2_I3C_H_ #include "S32Z2_COMMON.h" /* ---------------------------------------------------------------------------- -- I3C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer * @{ */ /** I3C - Register Layout Typedef */ typedef struct { __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ uint8_t RESERVED_1[8]; __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ uint8_t RESERVED_2[4]; union { /* offset: 0x48 */ __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0x48 */ __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ } SRDATAH_MRDATAH; uint8_t RESERVED_3[8]; union { /* offset: 0x54 */ __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ } SWDATA_B_H; uint8_t RESERVED_4[4]; __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ uint8_t RESERVED_5[12]; uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ uint8_t RESERVED_6[8]; __I uint32_t SMSGLAST; /**< Target Message Last Matched, offset: 0x7C */ uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ uint8_t RESERVED_7[4]; __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ uint8_t RESERVED_8[8]; __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ uint8_t RESERVED_9[8]; union { /* offset: 0xCC */ __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ } MWDATA_B1_H1; union { /* offset: 0xD0 */ __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ } MWMSG_SDR; __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ uint8_t RESERVED_10[72]; __IO uint32_t SMAPCTRL1; /**< Map Feature Control 1, offset: 0x120 */ uint8_t RESERVED_11[3788]; __IO uint32_t SELFRESET; /**< Self Reset, offset: 0xFF0 */ } I3C_Type, *I3C_MemMapPtr; /** Number of instances of the I3C module. */ #define I3C_INSTANCE_COUNT (1u) /* I3C - Peripheral instance base addresses */ /** Peripheral I3C_0 base address */ #define IP_I3C_0_BASE (0x401D0000u) /** Peripheral I3C_0 base pointer */ #define IP_I3C_0 ((I3C_Type *)IP_I3C_0_BASE) /** Array initializer of I3C peripheral base addresses */ #define IP_I3C_BASE_ADDRS { IP_I3C_0_BASE } /** Array initializer of I3C peripheral base pointers */ #define IP_I3C_BASE_PTRS { IP_I3C_0 } /* ---------------------------------------------------------------------------- -- I3C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I3C_Register_Masks I3C Register Masks * @{ */ /*! @name MCONFIG - Controller Configuration */ /*! @{ */ #define I3C_MCONFIG_MSTENA_MASK (0x3U) #define I3C_MCONFIG_MSTENA_SHIFT (0U) #define I3C_MCONFIG_MSTENA_WIDTH (2U) #define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) #define I3C_MCONFIG_DISTO_MASK (0x8U) #define I3C_MCONFIG_DISTO_SHIFT (3U) #define I3C_MCONFIG_DISTO_WIDTH (1U) #define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) #define I3C_MCONFIG_HKEEP_MASK (0x30U) #define I3C_MCONFIG_HKEEP_SHIFT (4U) #define I3C_MCONFIG_HKEEP_WIDTH (2U) #define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) #define I3C_MCONFIG_PPBAUD_MASK (0xF00U) #define I3C_MCONFIG_PPBAUD_SHIFT (8U) #define I3C_MCONFIG_PPBAUD_WIDTH (4U) #define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) #define I3C_MCONFIG_PPLOW_MASK (0xF000U) #define I3C_MCONFIG_PPLOW_SHIFT (12U) #define I3C_MCONFIG_PPLOW_WIDTH (4U) #define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) #define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) #define I3C_MCONFIG_ODBAUD_SHIFT (16U) #define I3C_MCONFIG_ODBAUD_WIDTH (8U) #define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) #define I3C_MCONFIG_SKEW_MASK (0xE000000U) #define I3C_MCONFIG_SKEW_SHIFT (25U) #define I3C_MCONFIG_SKEW_WIDTH (3U) #define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) #define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) #define I3C_MCONFIG_I2CBAUD_SHIFT (28U) #define I3C_MCONFIG_I2CBAUD_WIDTH (4U) #define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) /*! @} */ /*! @name SCONFIG - Target Configuration */ /*! @{ */ #define I3C_SCONFIG_SLVENA_MASK (0x1U) #define I3C_SCONFIG_SLVENA_SHIFT (0U) #define I3C_SCONFIG_SLVENA_WIDTH (1U) #define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) #define I3C_SCONFIG_NACK_MASK (0x2U) #define I3C_SCONFIG_NACK_SHIFT (1U) #define I3C_SCONFIG_NACK_WIDTH (1U) #define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) #define I3C_SCONFIG_MATCHSS_MASK (0x4U) #define I3C_SCONFIG_MATCHSS_SHIFT (2U) #define I3C_SCONFIG_MATCHSS_WIDTH (1U) #define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) #define I3C_SCONFIG_BAMATCH_MASK (0x3F0000U) #define I3C_SCONFIG_BAMATCH_SHIFT (16U) #define I3C_SCONFIG_BAMATCH_WIDTH (6U) #define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) #define I3C_SCONFIG_SADDR_MASK (0xFE000000U) #define I3C_SCONFIG_SADDR_SHIFT (25U) #define I3C_SCONFIG_SADDR_WIDTH (7U) #define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) /*! @} */ /*! @name SSTATUS - Target Status */ /*! @{ */ #define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) #define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) #define I3C_SSTATUS_STNOTSTOP_WIDTH (1U) #define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) #define I3C_SSTATUS_STMSG_MASK (0x2U) #define I3C_SSTATUS_STMSG_SHIFT (1U) #define I3C_SSTATUS_STMSG_WIDTH (1U) #define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) #define I3C_SSTATUS_STREQRD_MASK (0x8U) #define I3C_SSTATUS_STREQRD_SHIFT (3U) #define I3C_SSTATUS_STREQRD_WIDTH (1U) #define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) #define I3C_SSTATUS_STREQWR_MASK (0x10U) #define I3C_SSTATUS_STREQWR_SHIFT (4U) #define I3C_SSTATUS_STREQWR_WIDTH (1U) #define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) #define I3C_SSTATUS_START_MASK (0x100U) #define I3C_SSTATUS_START_SHIFT (8U) #define I3C_SSTATUS_START_WIDTH (1U) #define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) #define I3C_SSTATUS_MATCHED_MASK (0x200U) #define I3C_SSTATUS_MATCHED_SHIFT (9U) #define I3C_SSTATUS_MATCHED_WIDTH (1U) #define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) #define I3C_SSTATUS_STOP_MASK (0x400U) #define I3C_SSTATUS_STOP_SHIFT (10U) #define I3C_SSTATUS_STOP_WIDTH (1U) #define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) #define I3C_SSTATUS_RX_PEND_MASK (0x800U) #define I3C_SSTATUS_RX_PEND_SHIFT (11U) #define I3C_SSTATUS_RX_PEND_WIDTH (1U) #define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) #define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) #define I3C_SSTATUS_TXNOTFULL_WIDTH (1U) #define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) #define I3C_SSTATUS_ERRWARN_MASK (0x8000U) #define I3C_SSTATUS_ERRWARN_SHIFT (15U) #define I3C_SSTATUS_ERRWARN_WIDTH (1U) #define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) /*! @} */ /*! @name SINTSET - Target Interrupt Set */ /*! @{ */ #define I3C_SINTSET_START_MASK (0x100U) #define I3C_SINTSET_START_SHIFT (8U) #define I3C_SINTSET_START_WIDTH (1U) #define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) #define I3C_SINTSET_MATCHED_MASK (0x200U) #define I3C_SINTSET_MATCHED_SHIFT (9U) #define I3C_SINTSET_MATCHED_WIDTH (1U) #define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) #define I3C_SINTSET_STOP_MASK (0x400U) #define I3C_SINTSET_STOP_SHIFT (10U) #define I3C_SINTSET_STOP_WIDTH (1U) #define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) #define I3C_SINTSET_RXPEND_MASK (0x800U) #define I3C_SINTSET_RXPEND_SHIFT (11U) #define I3C_SINTSET_RXPEND_WIDTH (1U) #define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) #define I3C_SINTSET_TXSEND_MASK (0x1000U) #define I3C_SINTSET_TXSEND_SHIFT (12U) #define I3C_SINTSET_TXSEND_WIDTH (1U) #define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) #define I3C_SINTSET_ERRWARN_MASK (0x8000U) #define I3C_SINTSET_ERRWARN_SHIFT (15U) #define I3C_SINTSET_ERRWARN_WIDTH (1U) #define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) /*! @} */ /*! @name SINTCLR - Target Interrupt Clear */ /*! @{ */ #define I3C_SINTCLR_START_MASK (0x100U) #define I3C_SINTCLR_START_SHIFT (8U) #define I3C_SINTCLR_START_WIDTH (1U) #define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) #define I3C_SINTCLR_MATCHED_MASK (0x200U) #define I3C_SINTCLR_MATCHED_SHIFT (9U) #define I3C_SINTCLR_MATCHED_WIDTH (1U) #define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) #define I3C_SINTCLR_STOP_MASK (0x400U) #define I3C_SINTCLR_STOP_SHIFT (10U) #define I3C_SINTCLR_STOP_WIDTH (1U) #define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) #define I3C_SINTCLR_RXPEND_MASK (0x800U) #define I3C_SINTCLR_RXPEND_SHIFT (11U) #define I3C_SINTCLR_RXPEND_WIDTH (1U) #define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) #define I3C_SINTCLR_TXSEND_MASK (0x1000U) #define I3C_SINTCLR_TXSEND_SHIFT (12U) #define I3C_SINTCLR_TXSEND_WIDTH (1U) #define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) #define I3C_SINTCLR_ERRWARN_MASK (0x8000U) #define I3C_SINTCLR_ERRWARN_SHIFT (15U) #define I3C_SINTCLR_ERRWARN_WIDTH (1U) #define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) /*! @} */ /*! @name SINTMASKED - Target Interrupt Mask */ /*! @{ */ #define I3C_SINTMASKED_START_MASK (0x100U) #define I3C_SINTMASKED_START_SHIFT (8U) #define I3C_SINTMASKED_START_WIDTH (1U) #define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) #define I3C_SINTMASKED_MATCHED_MASK (0x200U) #define I3C_SINTMASKED_MATCHED_SHIFT (9U) #define I3C_SINTMASKED_MATCHED_WIDTH (1U) #define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) #define I3C_SINTMASKED_STOP_MASK (0x400U) #define I3C_SINTMASKED_STOP_SHIFT (10U) #define I3C_SINTMASKED_STOP_WIDTH (1U) #define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) #define I3C_SINTMASKED_RXPEND_MASK (0x800U) #define I3C_SINTMASKED_RXPEND_SHIFT (11U) #define I3C_SINTMASKED_RXPEND_WIDTH (1U) #define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) #define I3C_SINTMASKED_TXSEND_MASK (0x1000U) #define I3C_SINTMASKED_TXSEND_SHIFT (12U) #define I3C_SINTMASKED_TXSEND_WIDTH (1U) #define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) #define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_SINTMASKED_ERRWARN_SHIFT (15U) #define I3C_SINTMASKED_ERRWARN_WIDTH (1U) #define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) /*! @} */ /*! @name SERRWARN - Target Errors and Warnings */ /*! @{ */ #define I3C_SERRWARN_ORUN_MASK (0x1U) #define I3C_SERRWARN_ORUN_SHIFT (0U) #define I3C_SERRWARN_ORUN_WIDTH (1U) #define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) #define I3C_SERRWARN_URUN_MASK (0x2U) #define I3C_SERRWARN_URUN_SHIFT (1U) #define I3C_SERRWARN_URUN_WIDTH (1U) #define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) #define I3C_SERRWARN_URUNNACK_MASK (0x4U) #define I3C_SERRWARN_URUNNACK_SHIFT (2U) #define I3C_SERRWARN_URUNNACK_WIDTH (1U) #define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) #define I3C_SERRWARN_TERM_MASK (0x8U) #define I3C_SERRWARN_TERM_SHIFT (3U) #define I3C_SERRWARN_TERM_WIDTH (1U) #define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) #define I3C_SERRWARN_INVSTART_MASK (0x10U) #define I3C_SERRWARN_INVSTART_SHIFT (4U) #define I3C_SERRWARN_INVSTART_WIDTH (1U) #define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) #define I3C_SERRWARN_SPAR_MASK (0x100U) #define I3C_SERRWARN_SPAR_SHIFT (8U) #define I3C_SERRWARN_SPAR_WIDTH (1U) #define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) #define I3C_SERRWARN_OREAD_MASK (0x10000U) #define I3C_SERRWARN_OREAD_SHIFT (16U) #define I3C_SERRWARN_OREAD_WIDTH (1U) #define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) #define I3C_SERRWARN_OWRITE_MASK (0x20000U) #define I3C_SERRWARN_OWRITE_SHIFT (17U) #define I3C_SERRWARN_OWRITE_WIDTH (1U) #define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) /*! @} */ /*! @name SDMACTRL - Target DMA Control */ /*! @{ */ #define I3C_SDMACTRL_DMAFB_MASK (0x3U) #define I3C_SDMACTRL_DMAFB_SHIFT (0U) #define I3C_SDMACTRL_DMAFB_WIDTH (2U) #define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) #define I3C_SDMACTRL_DMATB_MASK (0xCU) #define I3C_SDMACTRL_DMATB_SHIFT (2U) #define I3C_SDMACTRL_DMATB_WIDTH (2U) #define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) #define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) #define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) #define I3C_SDMACTRL_DMAWIDTH_WIDTH (2U) #define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) /*! @} */ /*! @name SDATACTRL - Target Data Control */ /*! @{ */ #define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) #define I3C_SDATACTRL_FLUSHTB_WIDTH (1U) #define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) #define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) #define I3C_SDATACTRL_FLUSHFB_WIDTH (1U) #define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) #define I3C_SDATACTRL_UNLOCK_MASK (0x8U) #define I3C_SDATACTRL_UNLOCK_SHIFT (3U) #define I3C_SDATACTRL_UNLOCK_WIDTH (1U) #define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) #define I3C_SDATACTRL_TXTRIG_MASK (0x30U) #define I3C_SDATACTRL_TXTRIG_SHIFT (4U) #define I3C_SDATACTRL_TXTRIG_WIDTH (2U) #define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) #define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) #define I3C_SDATACTRL_RXTRIG_SHIFT (6U) #define I3C_SDATACTRL_RXTRIG_WIDTH (2U) #define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) #define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) #define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) #define I3C_SDATACTRL_TXCOUNT_WIDTH (5U) #define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) #define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) #define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) #define I3C_SDATACTRL_RXCOUNT_WIDTH (5U) #define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) #define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_SDATACTRL_TXFULL_SHIFT (30U) #define I3C_SDATACTRL_TXFULL_WIDTH (1U) #define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) #define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) #define I3C_SDATACTRL_RXEMPTY_WIDTH (1U) #define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) /*! @} */ /*! @name SWDATAB - Target Write Data Byte */ /*! @{ */ #define I3C_SWDATAB_DATA_MASK (0xFFU) #define I3C_SWDATAB_DATA_SHIFT (0U) #define I3C_SWDATAB_DATA_WIDTH (8U) #define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) #define I3C_SWDATAB_END_MASK (0x100U) #define I3C_SWDATAB_END_SHIFT (8U) #define I3C_SWDATAB_END_WIDTH (1U) #define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) #define I3C_SWDATAB_END_ALSO_MASK (0x10000U) #define I3C_SWDATAB_END_ALSO_SHIFT (16U) #define I3C_SWDATAB_END_ALSO_WIDTH (1U) #define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) /*! @} */ /*! @name SWDATABE - Target Write Data Byte End */ /*! @{ */ #define I3C_SWDATABE_DATA_MASK (0xFFU) #define I3C_SWDATABE_DATA_SHIFT (0U) #define I3C_SWDATABE_DATA_WIDTH (8U) #define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) /*! @} */ /*! @name SWDATAH - Target Write Data Halfword */ /*! @{ */ #define I3C_SWDATAH_DATA0_MASK (0xFFU) #define I3C_SWDATAH_DATA0_SHIFT (0U) #define I3C_SWDATAH_DATA0_WIDTH (8U) #define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) #define I3C_SWDATAH_DATA1_MASK (0xFF00U) #define I3C_SWDATAH_DATA1_SHIFT (8U) #define I3C_SWDATAH_DATA1_WIDTH (8U) #define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) #define I3C_SWDATAH_END_MASK (0x10000U) #define I3C_SWDATAH_END_SHIFT (16U) #define I3C_SWDATAH_END_WIDTH (1U) #define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) /*! @} */ /*! @name SWDATAHE - Target Write Data Halfword End */ /*! @{ */ #define I3C_SWDATAHE_DATA0_MASK (0xFFU) #define I3C_SWDATAHE_DATA0_SHIFT (0U) #define I3C_SWDATAHE_DATA0_WIDTH (8U) #define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) #define I3C_SWDATAHE_DATA1_MASK (0xFF00U) #define I3C_SWDATAHE_DATA1_SHIFT (8U) #define I3C_SWDATAHE_DATA1_WIDTH (8U) #define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) /*! @} */ /*! @name SRDATAB - Target Read Data Byte */ /*! @{ */ #define I3C_SRDATAB_DATA0_MASK (0xFFU) #define I3C_SRDATAB_DATA0_SHIFT (0U) #define I3C_SRDATAB_DATA0_WIDTH (8U) #define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) /*! @} */ /*! @name MRDATAH - Controller Read Data Halfword */ /*! @{ */ #define I3C_MRDATAH_LSB_MASK (0xFFU) #define I3C_MRDATAH_LSB_SHIFT (0U) #define I3C_MRDATAH_LSB_WIDTH (8U) #define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) #define I3C_MRDATAH_MSB_MASK (0xFF00U) #define I3C_MRDATAH_MSB_SHIFT (8U) #define I3C_MRDATAH_MSB_WIDTH (8U) #define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) /*! @} */ /*! @name SRDATAH - Target Read Data Halfword */ /*! @{ */ #define I3C_SRDATAH_LSB_MASK (0xFFU) #define I3C_SRDATAH_LSB_SHIFT (0U) #define I3C_SRDATAH_LSB_WIDTH (8U) #define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) #define I3C_SRDATAH_MSB_MASK (0xFF00U) #define I3C_SRDATAH_MSB_SHIFT (8U) #define I3C_SRDATAH_MSB_WIDTH (8U) #define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) /*! @} */ /*! @name SWDATAB1 - Target Write Data Byte */ /*! @{ */ #define I3C_SWDATAB1_DATA_MASK (0xFFU) #define I3C_SWDATAB1_DATA_SHIFT (0U) #define I3C_SWDATAB1_DATA_WIDTH (8U) #define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) /*! @} */ /*! @name SCAPABILITIES2 - Target Capabilities 2 */ /*! @{ */ #define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) #define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) #define I3C_SCAPABILITIES2_I2C10B_WIDTH (1U) #define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) #define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) #define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) #define I3C_SCAPABILITIES2_I2CRST_WIDTH (1U) #define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) #define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) #define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) #define I3C_SCAPABILITIES2_I2CDEVID_WIDTH (1U) #define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) /*! @} */ /*! @name SCAPABILITIES - Target Capabilities */ /*! @{ */ #define I3C_SCAPABILITIES_MASTER_MASK (0x200U) #define I3C_SCAPABILITIES_MASTER_SHIFT (9U) #define I3C_SCAPABILITIES_MASTER_WIDTH (1U) #define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) #define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) #define I3C_SCAPABILITIES_SADDR_SHIFT (10U) #define I3C_SCAPABILITIES_SADDR_WIDTH (2U) #define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) #define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) #define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) #define I3C_SCAPABILITIES_EXTFIFO_WIDTH (3U) #define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) #define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) #define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) #define I3C_SCAPABILITIES_FIFOTX_WIDTH (2U) #define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) #define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) #define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) #define I3C_SCAPABILITIES_FIFORX_WIDTH (2U) #define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) #define I3C_SCAPABILITIES_INT_MASK (0x40000000U) #define I3C_SCAPABILITIES_INT_SHIFT (30U) #define I3C_SCAPABILITIES_INT_WIDTH (1U) #define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) #define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) #define I3C_SCAPABILITIES_DMA_SHIFT (31U) #define I3C_SCAPABILITIES_DMA_WIDTH (1U) #define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) /*! @} */ /*! @name SMSGLAST - Target Message Last Matched */ /*! @{ */ #define I3C_SMSGLAST_LASTSTATIC_MASK (0x10U) #define I3C_SMSGLAST_LASTSTATIC_SHIFT (4U) #define I3C_SMSGLAST_LASTSTATIC_WIDTH (1U) #define I3C_SMSGLAST_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGLAST_LASTSTATIC_SHIFT)) & I3C_SMSGLAST_LASTSTATIC_MASK) /*! @} */ /*! @name MCTRL - Controller Control */ /*! @{ */ #define I3C_MCTRL_REQUEST_MASK (0x7U) #define I3C_MCTRL_REQUEST_SHIFT (0U) #define I3C_MCTRL_REQUEST_WIDTH (3U) #define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) #define I3C_MCTRL_TYPE_MASK (0x30U) #define I3C_MCTRL_TYPE_SHIFT (4U) #define I3C_MCTRL_TYPE_WIDTH (2U) #define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) #define I3C_MCTRL_DIR_MASK (0x100U) #define I3C_MCTRL_DIR_SHIFT (8U) #define I3C_MCTRL_DIR_WIDTH (1U) #define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) #define I3C_MCTRL_ADDR_MASK (0xFE00U) #define I3C_MCTRL_ADDR_SHIFT (9U) #define I3C_MCTRL_ADDR_WIDTH (7U) #define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) #define I3C_MCTRL_RDTERM_MASK (0xFF0000U) #define I3C_MCTRL_RDTERM_SHIFT (16U) #define I3C_MCTRL_RDTERM_WIDTH (8U) #define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) /*! @} */ /*! @name MSTATUS - Controller Status */ /*! @{ */ #define I3C_MSTATUS_STATE_MASK (0x7U) #define I3C_MSTATUS_STATE_SHIFT (0U) #define I3C_MSTATUS_STATE_WIDTH (3U) #define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) #define I3C_MSTATUS_BETWEEN_MASK (0x10U) #define I3C_MSTATUS_BETWEEN_SHIFT (4U) #define I3C_MSTATUS_BETWEEN_WIDTH (1U) #define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) #define I3C_MSTATUS_NACKED_MASK (0x20U) #define I3C_MSTATUS_NACKED_SHIFT (5U) #define I3C_MSTATUS_NACKED_WIDTH (1U) #define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) #define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) #define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) #define I3C_MSTATUS_MCTRLDONE_WIDTH (1U) #define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) #define I3C_MSTATUS_COMPLETE_MASK (0x400U) #define I3C_MSTATUS_COMPLETE_SHIFT (10U) #define I3C_MSTATUS_COMPLETE_WIDTH (1U) #define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) #define I3C_MSTATUS_RXPEND_MASK (0x800U) #define I3C_MSTATUS_RXPEND_SHIFT (11U) #define I3C_MSTATUS_RXPEND_WIDTH (1U) #define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) #define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) #define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) #define I3C_MSTATUS_TXNOTFULL_WIDTH (1U) #define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) #define I3C_MSTATUS_ERRWARN_MASK (0x8000U) #define I3C_MSTATUS_ERRWARN_SHIFT (15U) #define I3C_MSTATUS_ERRWARN_WIDTH (1U) #define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) /*! @} */ /*! @name MINTSET - Controller Interrupt Set */ /*! @{ */ #define I3C_MINTSET_MCTRLDONE_MASK (0x200U) #define I3C_MINTSET_MCTRLDONE_SHIFT (9U) #define I3C_MINTSET_MCTRLDONE_WIDTH (1U) #define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) #define I3C_MINTSET_COMPLETE_MASK (0x400U) #define I3C_MINTSET_COMPLETE_SHIFT (10U) #define I3C_MINTSET_COMPLETE_WIDTH (1U) #define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) #define I3C_MINTSET_RXPEND_MASK (0x800U) #define I3C_MINTSET_RXPEND_SHIFT (11U) #define I3C_MINTSET_RXPEND_WIDTH (1U) #define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) #define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) #define I3C_MINTSET_TXNOTFULL_SHIFT (12U) #define I3C_MINTSET_TXNOTFULL_WIDTH (1U) #define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) #define I3C_MINTSET_ERRWARN_MASK (0x8000U) #define I3C_MINTSET_ERRWARN_SHIFT (15U) #define I3C_MINTSET_ERRWARN_WIDTH (1U) #define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) /*! @} */ /*! @name MINTCLR - Controller Interrupt Clear */ /*! @{ */ #define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) #define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) #define I3C_MINTCLR_MCTRLDONE_WIDTH (1U) #define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) #define I3C_MINTCLR_COMPLETE_MASK (0x400U) #define I3C_MINTCLR_COMPLETE_SHIFT (10U) #define I3C_MINTCLR_COMPLETE_WIDTH (1U) #define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) #define I3C_MINTCLR_RXPEND_MASK (0x800U) #define I3C_MINTCLR_RXPEND_SHIFT (11U) #define I3C_MINTCLR_RXPEND_WIDTH (1U) #define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) #define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) #define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) #define I3C_MINTCLR_TXNOTFULL_WIDTH (1U) #define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) #define I3C_MINTCLR_ERRWARN_MASK (0x8000U) #define I3C_MINTCLR_ERRWARN_SHIFT (15U) #define I3C_MINTCLR_ERRWARN_WIDTH (1U) #define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) /*! @} */ /*! @name MINTMASKED - Controller Interrupt Mask */ /*! @{ */ #define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) #define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) #define I3C_MINTMASKED_MCTRLDONE_WIDTH (1U) #define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) #define I3C_MINTMASKED_COMPLETE_MASK (0x400U) #define I3C_MINTMASKED_COMPLETE_SHIFT (10U) #define I3C_MINTMASKED_COMPLETE_WIDTH (1U) #define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) #define I3C_MINTMASKED_RXPEND_MASK (0x800U) #define I3C_MINTMASKED_RXPEND_SHIFT (11U) #define I3C_MINTMASKED_RXPEND_WIDTH (1U) #define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) #define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) #define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) #define I3C_MINTMASKED_TXNOTFULL_WIDTH (1U) #define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) #define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) #define I3C_MINTMASKED_ERRWARN_SHIFT (15U) #define I3C_MINTMASKED_ERRWARN_WIDTH (1U) #define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) /*! @} */ /*! @name MERRWARN - Controller Errors and Warnings */ /*! @{ */ #define I3C_MERRWARN_NACK_MASK (0x4U) #define I3C_MERRWARN_NACK_SHIFT (2U) #define I3C_MERRWARN_NACK_WIDTH (1U) #define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) #define I3C_MERRWARN_WRABT_MASK (0x8U) #define I3C_MERRWARN_WRABT_SHIFT (3U) #define I3C_MERRWARN_WRABT_WIDTH (1U) #define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) #define I3C_MERRWARN_OREAD_MASK (0x10000U) #define I3C_MERRWARN_OREAD_SHIFT (16U) #define I3C_MERRWARN_OREAD_WIDTH (1U) #define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) #define I3C_MERRWARN_OWRITE_MASK (0x20000U) #define I3C_MERRWARN_OWRITE_SHIFT (17U) #define I3C_MERRWARN_OWRITE_WIDTH (1U) #define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) #define I3C_MERRWARN_MSGERR_MASK (0x40000U) #define I3C_MERRWARN_MSGERR_SHIFT (18U) #define I3C_MERRWARN_MSGERR_WIDTH (1U) #define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) #define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) #define I3C_MERRWARN_TIMEOUT_SHIFT (20U) #define I3C_MERRWARN_TIMEOUT_WIDTH (1U) #define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) /*! @} */ /*! @name MDMACTRL - Controller DMA Control */ /*! @{ */ #define I3C_MDMACTRL_DMAFB_MASK (0x3U) #define I3C_MDMACTRL_DMAFB_SHIFT (0U) #define I3C_MDMACTRL_DMAFB_WIDTH (2U) #define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) #define I3C_MDMACTRL_DMATB_MASK (0xCU) #define I3C_MDMACTRL_DMATB_SHIFT (2U) #define I3C_MDMACTRL_DMATB_WIDTH (2U) #define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) #define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) #define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) #define I3C_MDMACTRL_DMAWIDTH_WIDTH (2U) #define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) /*! @} */ /*! @name MDATACTRL - Controller Data Control */ /*! @{ */ #define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) #define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) #define I3C_MDATACTRL_FLUSHTB_WIDTH (1U) #define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) #define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) #define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) #define I3C_MDATACTRL_FLUSHFB_WIDTH (1U) #define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) #define I3C_MDATACTRL_UNLOCK_MASK (0x8U) #define I3C_MDATACTRL_UNLOCK_SHIFT (3U) #define I3C_MDATACTRL_UNLOCK_WIDTH (1U) #define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) #define I3C_MDATACTRL_TXTRIG_MASK (0x30U) #define I3C_MDATACTRL_TXTRIG_SHIFT (4U) #define I3C_MDATACTRL_TXTRIG_WIDTH (2U) #define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) #define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) #define I3C_MDATACTRL_RXTRIG_SHIFT (6U) #define I3C_MDATACTRL_RXTRIG_WIDTH (2U) #define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) #define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) #define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) #define I3C_MDATACTRL_TXCOUNT_WIDTH (5U) #define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) #define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) #define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) #define I3C_MDATACTRL_RXCOUNT_WIDTH (5U) #define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) #define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) #define I3C_MDATACTRL_TXFULL_SHIFT (30U) #define I3C_MDATACTRL_TXFULL_WIDTH (1U) #define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) #define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) #define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) #define I3C_MDATACTRL_RXEMPTY_WIDTH (1U) #define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) /*! @} */ /*! @name MWDATAB - Controller Write Data Byte */ /*! @{ */ #define I3C_MWDATAB_VALUE_MASK (0xFFU) #define I3C_MWDATAB_VALUE_SHIFT (0U) #define I3C_MWDATAB_VALUE_WIDTH (8U) #define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) #define I3C_MWDATAB_END_MASK (0x100U) #define I3C_MWDATAB_END_SHIFT (8U) #define I3C_MWDATAB_END_WIDTH (1U) #define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) #define I3C_MWDATAB_END_ALSO_MASK (0x10000U) #define I3C_MWDATAB_END_ALSO_SHIFT (16U) #define I3C_MWDATAB_END_ALSO_WIDTH (1U) #define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) /*! @} */ /*! @name MWDATABE - Controller Write Data Byte End */ /*! @{ */ #define I3C_MWDATABE_VALUE_MASK (0xFFU) #define I3C_MWDATABE_VALUE_SHIFT (0U) #define I3C_MWDATABE_VALUE_WIDTH (8U) #define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) /*! @} */ /*! @name MWDATAH - Controller Write Data Halfword */ /*! @{ */ #define I3C_MWDATAH_DATA0_MASK (0xFFU) #define I3C_MWDATAH_DATA0_SHIFT (0U) #define I3C_MWDATAH_DATA0_WIDTH (8U) #define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) #define I3C_MWDATAH_DATA1_MASK (0xFF00U) #define I3C_MWDATAH_DATA1_SHIFT (8U) #define I3C_MWDATAH_DATA1_WIDTH (8U) #define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) #define I3C_MWDATAH_END_MASK (0x10000U) #define I3C_MWDATAH_END_SHIFT (16U) #define I3C_MWDATAH_END_WIDTH (1U) #define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) /*! @} */ /*! @name MWDATAHE - Controller Write Data Halfword End */ /*! @{ */ #define I3C_MWDATAHE_DATA0_MASK (0xFFU) #define I3C_MWDATAHE_DATA0_SHIFT (0U) #define I3C_MWDATAHE_DATA0_WIDTH (8U) #define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) #define I3C_MWDATAHE_DATA1_MASK (0xFF00U) #define I3C_MWDATAHE_DATA1_SHIFT (8U) #define I3C_MWDATAHE_DATA1_WIDTH (8U) #define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) /*! @} */ /*! @name MRDATAB - Controller Read Data Byte */ /*! @{ */ #define I3C_MRDATAB_VALUE_MASK (0xFFU) #define I3C_MRDATAB_VALUE_SHIFT (0U) #define I3C_MRDATAB_VALUE_WIDTH (8U) #define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) /*! @} */ /*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ /*! @{ */ #define I3C_MWDATAB1_VALUE_MASK (0xFFU) #define I3C_MWDATAB1_VALUE_SHIFT (0U) #define I3C_MWDATAB1_VALUE_WIDTH (8U) #define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) /*! @} */ /*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ /*! @{ */ #define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) #define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) #define I3C_MWMSG_SDR_CONTROL_DIR_WIDTH (1U) #define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) #define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) #define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) #define I3C_MWMSG_SDR_CONTROL_ADDR_WIDTH (7U) #define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) #define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) #define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) #define I3C_MWMSG_SDR_CONTROL_END_WIDTH (1U) #define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) #define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) #define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) #define I3C_MWMSG_SDR_CONTROL_I2C_WIDTH (1U) #define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) #define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) #define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) #define I3C_MWMSG_SDR_CONTROL_LEN_WIDTH (5U) #define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) /*! @} */ /*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ /*! @{ */ #define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) #define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) #define I3C_MWMSG_SDR_DATA_DATA16B_WIDTH (16U) #define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) /*! @} */ /*! @name MRMSG_SDR - Controller Read Message in SDR mode */ /*! @{ */ #define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) #define I3C_MRMSG_SDR_DATA_SHIFT (0U) #define I3C_MRMSG_SDR_DATA_WIDTH (16U) #define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) /*! @} */ /*! @name SMAPCTRL1 - Map Feature Control 1 */ /*! @{ */ #define I3C_SMAPCTRL1_ENA_MASK (0x1U) #define I3C_SMAPCTRL1_ENA_SHIFT (0U) #define I3C_SMAPCTRL1_ENA_WIDTH (1U) #define I3C_SMAPCTRL1_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ENA_SHIFT)) & I3C_SMAPCTRL1_ENA_MASK) #define I3C_SMAPCTRL1_ADDR_MASK (0xFEU) #define I3C_SMAPCTRL1_ADDR_SHIFT (1U) #define I3C_SMAPCTRL1_ADDR_WIDTH (7U) #define I3C_SMAPCTRL1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_ADDR_SHIFT)) & I3C_SMAPCTRL1_ADDR_MASK) #define I3C_SMAPCTRL1_MAPSA_MASK (0x100U) #define I3C_SMAPCTRL1_MAPSA_SHIFT (8U) #define I3C_SMAPCTRL1_MAPSA_WIDTH (1U) #define I3C_SMAPCTRL1_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_MAPSA_SHIFT)) & I3C_SMAPCTRL1_MAPSA_MASK) #define I3C_SMAPCTRL1_NACK_MASK (0x1000U) #define I3C_SMAPCTRL1_NACK_SHIFT (12U) #define I3C_SMAPCTRL1_NACK_WIDTH (1U) #define I3C_SMAPCTRL1_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL1_NACK_SHIFT)) & I3C_SMAPCTRL1_NACK_MASK) /*! @} */ /*! @name SELFRESET - Self Reset */ /*! @{ */ #define I3C_SELFRESET_RST_MASK (0x1U) #define I3C_SELFRESET_RST_SHIFT (0U) #define I3C_SELFRESET_RST_WIDTH (1U) #define I3C_SELFRESET_RST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_RST_SHIFT)) & I3C_SELFRESET_RST_MASK) #define I3C_SELFRESET_KEY_MASK (0xFFFFFF00U) #define I3C_SELFRESET_KEY_SHIFT (8U) #define I3C_SELFRESET_KEY_WIDTH (24U) #define I3C_SELFRESET_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SELFRESET_KEY_SHIFT)) & I3C_SELFRESET_KEY_MASK) /*! @} */ /*! * @} */ /* end of group I3C_Register_Masks */ /*! * @} */ /* end of group I3C_Peripheral_Access_Layer */ #endif /* #if !defined(S32Z2_I3C_H_) */