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Searched refs:I3C_MWMSG_DDR_CONTROL2_END (Results 1 – 25 of 49) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h14406 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h14406 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h14406 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h14406 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h17542 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h17542 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h17542 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h17546 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h17546 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h17546 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h24058 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h24058 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h26691 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
DMIMXRT735S_cm33_core1.h26735 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h24057 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h26735 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
DMIMXRT758S_hifi1.h26691 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h26515 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h26485 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h26691 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
DMIMXRT798S_cm33_core1.h26735 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h21213 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
DMCXW727C_cm33_core1.h29525 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h35343 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h35343 #define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONT… macro

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