Home
last modified time | relevance | path

Searched refs:I3C1FCLKSTCDIV (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c1437 ((SYSCON->I3C1FCLKSTCDIV & SYSCON_I3C1FCLKSTCDIV_DIV_MASK) + 1U)); in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c1437 ((SYSCON->I3C1FCLKSTCDIV & SYSCON_I3C1FCLKSTCDIV_DIV_MASK) + 1U)); in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c1437 ((SYSCON->I3C1FCLKSTCDIV & SYSCON_I3C1FCLKSTCDIV_DIV_MASK) + 1U)); in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c1437 ((SYSCON->I3C1FCLKSTCDIV & SYSCON_I3C1FCLKSTCDIV_DIV_MASK) + 1U)); in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h69721 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
DMCXN546_cm33_core1.h69721 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h69721 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
DMCXN547_cm33_core1.h69721 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h72387 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
DMCXN947_cm33_core0.h72387 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h72387 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member
DMCXN946_cm33_core1.h72387 …__IO uint32_t I3C1FCLKSTCDIV; /**< I3C1 FCLK_STC Clock Divider, offset: 0xB38 */ member