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Searched refs:I3C0FCLKSTCDIV (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/drivers/
Dfsl_clock.c1436 div = ((id == 0U) ? ((SYSCON->I3C0FCLKSTCDIV & SYSCON_I3C0FCLKSTCDIV_DIV_MASK) + 1U) : in CLOCK_GetI3cSTCClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h2774 __IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 fclk STC divider, offset: 0x788 */ member
DMIMXRT685S_cm33.h8504 __IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 fclk STC divider, offset: 0x788 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h8504 __IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 fclk STC divider, offset: 0x788 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core1.h69630 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
DMCXN546_cm33_core0.h69630 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h72296 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
DMCXN946_cm33_core1.h72296 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core1.h69630 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
DMCXN547_cm33_core0.h69630 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h72296 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member
DMCXN947_cm33_core0.h72296 …__IO uint32_t I3C0FCLKSTCDIV; /**< I3C0 FCLK_STC Clock Divider, offset: 0x538 */ member