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Searched refs:FMU_FCNFG_ERSIEN1_MASK (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h6159 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
6165 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h6159 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
6165 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h6159 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
6165 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h6159 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
6165 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h9214 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9220 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h9214 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9220 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h9214 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9220 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h9218 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9224 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h9218 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9224 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h9218 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9224 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h9395 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
9401 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h11564 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
11570 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h16246 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
16252 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h16216 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
16222 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h12067 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
12073 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
DMCXW727C_cm33_core1.h20415 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
20421 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h24954 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
24960 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
DMCXN546_cm33_core1.h24954 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
24960 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h24954 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
24960 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
DMCXN547_cm33_core1.h24954 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
24960 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h25000 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
25006 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
DMCXN947_cm33_core0.h25000 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
25006 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h25000 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
25006 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)
DMCXN946_cm33_core1.h25000 #define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) macro
25006 … (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK)