Home
last modified time | relevance | path

Searched refs:FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h8746 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
8752 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h8746 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
8752 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h8746 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
8752 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h8746 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
8752 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h11801 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
11807 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h11801 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
11807 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h11801 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
11807 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h11805 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
11811 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h11805 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
11811 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h11805 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
11811 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h18849 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
18855 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h18819 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
18825 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h27557 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27563 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
DMCXN546_cm33_core1.h27557 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27563 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h27557 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27563 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
DMCXN547_cm33_core1.h27557 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27563 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h27603 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27609 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
DMCXN947_cm33_core0.h27603 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27609 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h27603 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27609 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)
DMCXN946_cm33_core1.h27603 #define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) macro
27609 …(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK)