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Searched refs:FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h8296 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
8299 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h8296 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
8299 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h8296 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
8299 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h8296 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
8299 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h11351 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
11354 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h11351 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
11354 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h11351 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
11354 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h11355 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
11358 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h11355 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
11358 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h11355 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
11358 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h18399 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
18402 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h18369 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
18372 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h27107 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27110 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
DMCXN546_cm33_core1.h27107 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27110 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h27107 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27110 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
DMCXN547_cm33_core1.h27107 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27110 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h27153 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27156 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
DMCXN947_cm33_core0.h27153 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27156 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h27153 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27156 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)
DMCXN946_cm33_core1.h27153 #define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) macro
27156 …(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK)