Home
last modified time | relevance | path

Searched refs:FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h8363 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
8366 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h8363 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
8366 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h8363 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
8366 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h8363 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
8366 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h11418 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
11421 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h11418 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
11421 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h11418 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
11421 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h11422 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
11425 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h11422 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
11425 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h11422 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
11425 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h18466 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
18469 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h18436 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
18439 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h27174 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27177 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
DMCXN546_cm33_core1.h27174 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27177 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h27174 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27177 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
DMCXN547_cm33_core1.h27174 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27177 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h27220 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27223 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
DMCXN947_cm33_core0.h27220 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27223 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h27220 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27223 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)
DMCXN946_cm33_core1.h27220 #define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) macro
27223 …(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK)