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Searched refs:FMUTEST_R_SME_WHV0_SMEWHV0_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h8390 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
8393 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h8390 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
8393 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h8390 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
8393 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h8390 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
8393 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h11445 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
11448 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h11445 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
11448 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h11445 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
11448 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h11449 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
11452 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h11449 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
11452 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h11449 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
11452 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h18493 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
18496 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h18463 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
18466 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h27201 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27204 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
DMCXN546_cm33_core1.h27201 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27204 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h27201 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27204 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
DMCXN547_cm33_core1.h27201 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27204 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h27247 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27250 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
DMCXN947_cm33_core0.h27247 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27250 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h27247 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27250 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)
DMCXN946_cm33_core1.h27247 #define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) macro
27250 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK)