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Searched refs:FMUTEST_R_C_MISR0_CTRLSIG0_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h8435 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
8438 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h8435 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
8438 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h8435 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
8438 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h8435 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
8438 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h11490 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
11493 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h11490 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
11493 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h11490 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
11493 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h11494 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
11497 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h11494 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
11497 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h11494 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
11497 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h18538 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
18541 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h18508 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
18511 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h27246 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27249 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
DMCXN546_cm33_core1.h27246 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27249 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h27246 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27249 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
DMCXN547_cm33_core1.h27246 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27249 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h27292 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27295 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
DMCXN947_cm33_core0.h27292 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27295 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h27292 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27295 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)
DMCXN946_cm33_core1.h27292 #define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) macro
27295 …(uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK)