Home
last modified time | relevance | path

Searched refs:FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (Results 1 – 25 of 91) sorted by relevance

1234

/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.c524 … FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_ARDSEQID_MASK); in FLEXSPI_SetFlashConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7617 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
7620 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
DMIMXRT685S_cm33.h13594 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
13597 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13921 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
13924 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h16415 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
16418 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13594 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
13597 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h13577 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
13580 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
DMIMXRT595S_cm33.h20175 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
20178 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19734 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
19737 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h14135 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
14138 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h14135 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
14138 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19754 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
19757 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20694 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
20697 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21864 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
21867 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h21479 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
21482 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21866 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
21869 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h20171 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
20174 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h22241 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
22244 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h20174 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
20177 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h23099 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
23102 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h14134 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
14137 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h23027 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
23030 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h23418 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
23421 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h23418 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
23421 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h37482 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) macro
37485 …(((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)

1234