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Searched refs:FLEXSPI0 (Results 1 – 25 of 42) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/iped/
Dfsl_iped.c278 IPED_SetLock(FLEXSPI0, config->option.iped_region); in IPED_Configure()
398 IPED_SetPrinceRounds(FLEXSPI0, kIPED_PrinceRounds12); in IPED_Reconfigure()
411 …status = IPED_SetRegionAddressRange(FLEXSPI0, (iped_region_t)region, ipedStart[region], ipedEnd[re… in IPED_Reconfigure()
431 status = IPED_SetRegionIV(FLEXSPI0, (iped_region_t)region, (uint8_t *)IvReg); in IPED_Reconfigure()
440 IPED_SetLock(FLEXSPI0, region); in IPED_Reconfigure()
448 …IPED_SetRegionAddressRange(FLEXSPI0, (iped_region_t)config->option.iped_region, config->start, con… in IPED_Reconfigure()
464 … status = IPED_SetRegionIV(FLEXSPI0, (iped_region_t)config->option.iped_region, (uint8_t *)IvReg); in IPED_Reconfigure()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt595/
Dclock_config.c72 if (FLEXSPI0 == base) in BOARD_SetFlexspiClock()
239 BOARD_SetFlexspiClock(FLEXSPI0, 0U, 2U); in BOARD_BootClockRUN()
Dboard.c363 if (base == FLEXSPI0) in BOARD_SetFlexspiClock()
426 BOARD_SetFlexspiClock(FLEXSPI0, 3U, 2U); in BOARD_FlexspiClockSafeConfig()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/
Dclock_config.c269 …BOARD_SetFlexspiClock(FLEXSPI0, 5U, freq_divider - 1, 0U); /* flexspi0's clock is CM33_PLATCLK / d… in BOARD_BootClockRUN()
309 …BOARD_SetFlexspiClock(FLEXSPI0, 5U, freq_divider - 1, 0U); /* flexspi0's clock is CM33_PLATCLK / d… in BOARD_ResumeClockInit()
940 …BOARD_SetFlexspiClock(FLEXSPI0, 5U, freq_divider - 1, 0U); /* flexspi0's clock is CM33_PLATCLK / d… in BOARD_SwitchDriveMode()
Dboard.h73 #define BOARD_FLEXSPI_CONNECT_TO_NOR_FLASH FLEXSPI0
Dboard.c1567 if (base == FLEXSPI0) in BOARD_SetFlexspiClock()
1624 …BOARD_SetFlexspiClock(FLEXSPI0, 6U, freq_divider - 1, 0U); /* flexspi0's clock is FRO(192 MHz) / d… in BOARD_FlexspiClockSafeConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c623 while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) && in AT_QUICKACCESS_SECTION_CODE()
624 ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U))) in AT_QUICKACCESS_SECTION_CODE()
628 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
706 initFlexSPI(FLEXSPI0); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c623 while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) && in AT_QUICKACCESS_SECTION_CODE()
624 ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U))) in AT_QUICKACCESS_SECTION_CODE()
628 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
706 initFlexSPI(FLEXSPI0); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c623 while (!(((FLEXSPI0->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) != 0U) && in AT_QUICKACCESS_SECTION_CODE()
624 ((FLEXSPI0->STS0 & FLEXSPI_STS0_SEQIDLE_MASK) != 0U))) in AT_QUICKACCESS_SECTION_CODE()
628 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
706 initFlexSPI(FLEXSPI0); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/mimxrt595/
Dmflash_drv.h23 #define MFLASH_FLEXSPI (FLEXSPI0)
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.c1223 #if defined(FLEXSPI0)
1227 s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); in FLEXSPI0_DriverIRQHandler()
1273 s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); in FLEXSPI0_FLEXSPI1_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp_features.h494 (((x) == FLEXSPI0) ? (1024) : \
DMIMXRT595S_cm33_features.h500 (((x) == FLEXSPI0) ? (1024) : \
DMIMXRT595S_cm33.h20694 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20708 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
20717 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20725 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S_features.h496 (((x) == FLEXSPI0) ? (1024) : \
DMIMXRT533S.h20690 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20704 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
20713 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20721 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S_features.h500 (((x) == FLEXSPI0) ? (1024) : \
DMIMXRT555S.h20693 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20707 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
20716 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
20724 #define FLEXSPI_BASE_PTRS { FLEXSPI0, FLEXSPI1 }
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/
DREADME.md124 In deep sleep, only the defined SRAM partition and the FLEXSPI0 SRAM are retained, i.e., the memory…
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h15015 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
15021 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
15030 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
15034 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h15015 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
15021 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
15030 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
15034 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h15014 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
15020 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
15029 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
15033 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h24726 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
24732 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
24741 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
24745 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
DMCXN546_cm33_core1.h24726 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
24732 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
24741 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
24745 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h24726 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
24732 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }
24741 #define FLEXSPI0 ((FLEXSPI_Type *)FLEXSPI0_BASE) macro
24745 #define FLEXSPI_BASE_PTRS { FLEXSPI0 }

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