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Searched refs:EMVSIM_RX_THD_RDT_MASK (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_emvsim.c214 rx_thd = (base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK); in smartcard_emvsim_StartReceiveData()
220 base->RX_THD = ((base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK) | context->rxFifoThreshold); in smartcard_emvsim_StartReceiveData()
455 if ((EMVSIM_RX_THD_RDT_MASK >> EMVSIM_RX_THD_RDT_SHIFT) < context->rxFifoThreshold) in SMARTCARD_EMVSIM_Init()
457 context->rxFifoThreshold = (EMVSIM_RX_THD_RDT_MASK >> EMVSIM_RX_THD_RDT_SHIFT); in SMARTCARD_EMVSIM_Init()
902 rx_thd = (base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK); in SMARTCARD_EMVSIM_IRQHandler()
1101 base->RX_THD = ((base->RX_THD & ~EMVSIM_RX_THD_RDT_MASK) | 1u); in SMARTCARD_EMVSIM_Control()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4591 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
4594 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4591 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
4594 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h5695 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
5698 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DK32L3A60_cm0plus.h4748 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
4751 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h9107 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
9109 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h9101 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
9103 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h16211 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16214 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMCXN546_cm33_core1.h16211 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16214 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h16211 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16214 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMCXN547_cm33_core1.h16211 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16214 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31412 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
31415 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMIMXRT1175_cm7.h31414 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
31417 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h31102 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
31105 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMIMXRT1165_cm4.h31100 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
31103 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31414 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
31417 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h16257 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16260 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMCXN947_cm33_core0.h16257 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16260 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h16257 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16260 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMCXN946_cm33_core1.h16257 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
16260 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h23322 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
23325 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h33105 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
33108 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
DMIMXRT1166_cm7.h33107 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
33110 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h33414 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
33417 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h33419 #define EMVSIM_RX_THD_RDT_MASK (0xFU) macro
33422 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)

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