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Searched refs:EMVSIM_GPCNT1_VAL_GPCNT1_MASK (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4971 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
4974 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4971 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
4974 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h6075 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
6078 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DK32L3A60_cm0plus.h5128 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
5131 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h9432 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
9434 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h9426 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
9428 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h16578 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16581 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMCXN546_cm33_core1.h16578 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16581 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h16578 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16581 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMCXN547_cm33_core1.h16578 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16581 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31779 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
31782 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMIMXRT1175_cm7.h31781 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
31784 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h31469 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
31472 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMIMXRT1165_cm4.h31467 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
31470 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31781 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
31784 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h16624 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16627 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMCXN947_cm33_core0.h16624 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16627 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h16624 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16627 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMCXN946_cm33_core1.h16624 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
16627 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h23702 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
23705 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h33472 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
33475 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMIMXRT1166_cm7.h33474 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
33477 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h33781 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
33784 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
DMIMXRT1173_cm7.h33783 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
33786 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h33786 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) macro
33789 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)

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