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Searched refs:EMVSIM_CTRL_RCVR_11_MASK (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_emvsim.c255 …base->CTRL &= ~(EMVSIM_CTRL_RCVR_11_MASK | EMVSIM_CTRL_XMT_CRC_LRC_MASK | EMVSIM_CTRL_LRC_EN_MASK | in smartcard_emvsim_SetTransferType()
294 …M_CTRL_RCV_EN_MASK | EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK | EMVSIM_CTRL_RCVR_11_MASK | in smartcard_emvsim_SetTransferType()
366 … base->CTRL |= (EMVSIM_CTRL_RCVR_11_MASK | EMVSIM_CTRL_CWT_EN_MASK | EMVSIM_CTRL_BWT_EN_MASK); in smartcard_emvsim_SetTransferType()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4367 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
4373 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4367 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
4373 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h5471 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
5477 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DK32L3A60_cm0plus.h4524 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
4530 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h8910 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
8916 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h8904 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
8910 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h15987 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
15993 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMCXN546_cm33_core1.h15987 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
15993 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h15987 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
15993 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMCXN547_cm33_core1.h15987 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
15993 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31188 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
31194 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMIMXRT1175_cm7.h31190 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
31196 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h30878 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
30884 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMIMXRT1165_cm4.h30876 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
30882 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31190 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
31196 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h16033 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
16039 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMCXN947_cm33_core0.h16033 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
16039 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h16033 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
16039 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMCXN946_cm33_core1.h16033 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
16039 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h23098 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
23104 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h32881 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
32887 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
DMIMXRT1166_cm7.h32883 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
32889 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h33190 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
33196 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h33195 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) macro
33201 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)

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