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Searched refs:DSPCPUCLKSEL_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h800 #define DSPCPUCLKSEL_OFFSET 0x444 macro
1023 …kDSP_BASE_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach DSP base cloc…
1024 …kMAIN_PLL_PFD0_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0…
1025 …kFRO0_DIV1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max cloc…
1026 …kMAIN_PLL_PFD1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD1…
1027 …kNONE_to_DSP = CLKCTL0_TUPLE_MUXA_NONE(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach NONE to DSP C…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h800 #define DSPCPUCLKSEL_OFFSET 0x444 macro
1023 …kDSP_BASE_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach DSP base cloc…
1024 …kMAIN_PLL_PFD0_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0…
1025 …kFRO0_DIV1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max cloc…
1026 …kMAIN_PLL_PFD1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD1…
1027 …kNONE_to_DSP = CLKCTL0_TUPLE_MUXA_NONE(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach NONE to DSP C…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h800 #define DSPCPUCLKSEL_OFFSET 0x444 macro
1023 …kDSP_BASE_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach DSP base cloc…
1024 …kMAIN_PLL_PFD0_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 1), /*!< Attach MAIN PLL PFD0…
1025 …kFRO0_DIV1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 2), /*!< Attach FRO0 Max cloc…
1026 …kMAIN_PLL_PFD1_to_DSP = CLKCTL0_TUPLE_MUXA(DSPCPUCLKSEL_OFFSET, 3), /*!< Attach MAIN PLL PFD1…
1027 …kNONE_to_DSP = CLKCTL0_TUPLE_MUXA_NONE(DSPCPUCLKSEL_OFFSET, 0), /*!< Attach NONE to DSP C…