Home
last modified time | relevance | path

Searched refs:DR (Results 1 – 25 of 77) sorted by relevance

1234

/hal_nxp-latest/mcux/mcux-sdk/drivers/igpio/
Dfsl_gpio.h117 base->DR |= mask; in GPIO_PortSet()
141 base->DR &= ~mask; in GPIO_PortClear()
165 base->DR ^= mask; in GPIO_PortToggle()
180 return (((base->DR) >> pin) & 0x1U); in GPIO_PinRead()
Dfsl_gpio.c123 base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ in GPIO_PinWrite()
131 base->DR |= (1UL << pin); /* Set pin output to high level.*/ in GPIO_PinWrite()
/hal_nxp-latest/mcux/mcux-sdk/drivers/afe/
Dfsl_afe.c242 base->DR[channel] = AFE_DR_DLY(value); in AFE_SetChannelPhaseDelayValue()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h995 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h13484 __I uint32_t DR; /**< GPC Debug Register, offset: 0x30 */ member
13509 #define GPC_DR_REG(base) ((base)->DR)
13728 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
13748 #define GPIO_DR_REG(base) ((base)->DR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h997 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h993 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h814 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h831 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Register, array offset: 0x2C, ar… member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h19721 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
19741 #define GPIO_DR_REG(base) ((base)->DR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h17035 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h14541 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h20374 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h20354 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h22498 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h21311 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h22500 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h22096 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h22876 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h31230 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h31228 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h31228 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
DMIMX8MN6_ca53.h31256 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h23662 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h23733 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member

1234