/hal_nxp-latest/mcux/mcux-sdk/drivers/igpio/ |
D | fsl_gpio.h | 117 base->DR |= mask; in GPIO_PortSet() 141 base->DR &= ~mask; in GPIO_PortClear() 165 base->DR ^= mask; in GPIO_PortToggle() 180 return (((base->DR) >> pin) & 0x1U); in GPIO_PinRead()
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D | fsl_gpio.c | 123 base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ in GPIO_PinWrite() 131 base->DR |= (1UL << pin); /* Set pin output to high level.*/ in GPIO_PinWrite()
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/hal_nxp-latest/mcux/mcux-sdk/drivers/afe/ |
D | fsl_afe.c | 242 base->DR[channel] = AFE_DR_DLY(value); in AFE_SetChannelPhaseDelayValue()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/ |
D | MKM14ZA5.h | 995 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
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/hal_nxp-latest/imx/devices/MCIMX6X/ |
D | MCIMX6X_M4.h | 13484 __I uint32_t DR; /**< GPC Debug Register, offset: 0x30 */ member 13509 #define GPC_DR_REG(base) ((base)->DR) 13728 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member 13748 #define GPIO_DR_REG(base) ((base)->DR)
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/ |
D | MKM33ZA5.h | 997 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/ |
D | MKM34ZA5.h | 993 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/ |
D | MKM35Z7.h | 814 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Regi… member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/ |
D | MKM34Z7.h | 831 …__IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Register, array offset: 0x2C, ar… member
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/hal_nxp-latest/imx/devices/MCIMX7D/ |
D | MCIMX7D_M4.h | 19721 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member 19741 #define GPIO_DR_REG(base) ((base)->DR)
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/ |
D | MIMXRT1015.h | 17035 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
D | MIMXRT1011.h | 14541 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
D | MIMXRT1021.h | 20374 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
D | MIMXRT1024.h | 20354 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
D | MIMXRT1041.h | 22498 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
D | MIMXRT1051.h | 21311 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
D | MIMXRT1042.h | 22500 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
D | MIMXRT1052.h | 22096 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
D | MIMXRT1061.h | 22876 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
D | MIMX8MN1_cm7.h | 31230 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
D | MIMX8MN2_cm7.h | 31228 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
D | MIMX8MN6_cm7.h | 31228 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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D | MIMX8MN6_ca53.h | 31256 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
D | MIMXRT1062.h | 23662 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
D | MIMXRT1064.h | 23733 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ member
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