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Searched refs:DMA_CH_INT_INT_MASK (Results 1 – 25 of 91) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/
Dfsl_ad_edma.c779 retval |= (((base->CH[channel].CH_INT & DMA_CH_INT_INT_MASK) >> DMA_CH_INT_INT_SHIFT) << 2U); in EDMA_AD_GetChannelStatusFlags()
809 base->CH[channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_AD_ClearChannelStatusFlags()
1372 handle->base->CH[handle->channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_AD_HandleIRQ()
Dfsl_edma.c807 retval |= (((base->CH[channel].CH_INT & DMA_CH_INT_INT_MASK) >> DMA_CH_INT_INT_SHIFT) << 2U); in EDMA_GetChannelStatusFlags()
837 base->CH[channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_ClearChannelStatusFlags()
1423 handle->base->CH[handle->channel].CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_HandleIRQ()
/hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/
Dfsl_edma.c2520 if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_HandleIRQ()
2522 handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_HandleIRQ()
2641 if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_DriverIRQHandler()
Dfsl_edma_core.h126 …MA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/
Dfsl_edma.c2527 if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_HandleIRQ()
2529 handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; in EDMA_HandleIRQ()
2648 if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) in EDMA_DriverIRQHandler()
Dfsl_edma_core.h126 …MA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK)
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2644 #define DMA_CH_INT_INT_MASK DMA_TCD_CH0_INT_INT_MASK macro
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h2174 #define DMA_CH_INT_INT_MASK EDMA3_TCD_CH_INT_INT_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h4301 #define DMA_CH_INT_INT_MASK (0x1U) macro
4307 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h4301 #define DMA_CH_INT_INT_MASK (0x1U) macro
4307 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h4301 #define DMA_CH_INT_INT_MASK (0x1U) macro
4307 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h4301 #define DMA_CH_INT_INT_MASK (0x1U) macro
4307 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h6512 #define DMA_CH_INT_INT_MASK (0x1U) macro
6518 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h6512 #define DMA_CH_INT_INT_MASK (0x1U) macro
6518 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h6512 #define DMA_CH_INT_INT_MASK (0x1U) macro
6518 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h6512 #define DMA_CH_INT_INT_MASK (0x1U) macro
6518 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h6512 #define DMA_CH_INT_INT_MASK (0x1U) macro
6518 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h6512 #define DMA_CH_INT_INT_MASK (0x1U) macro
6518 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h7267 #define DMA_CH_INT_INT_MASK (0x1U) macro
7273 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h18050 #define DMA_CH_INT_INT_MASK (0x1U) macro
18056 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
DMIMXRT735S_cm33_core1.h18088 #define DMA_CH_INT_INT_MASK (0x1U) macro
18094 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h9436 #define DMA_CH_INT_INT_MASK (0x1U) macro
9442 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h18088 #define DMA_CH_INT_INT_MASK (0x1U) macro
18094 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h12667 #define DMA_CH_INT_INT_MASK (0x1U) macro
12673 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h12637 #define DMA_CH_INT_INT_MASK (0x1U) macro
12643 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)

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