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Searched refs:DIGTMP_PPR_TPP4_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h11909 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
11915 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h11879 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
11885 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h14193 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14199 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
DMCXN546_cm33_core1.h14193 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14199 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h14193 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14199 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
DMCXN547_cm33_core1.h14193 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14199 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h14239 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14245 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
DMCXN947_cm33_core0.h14239 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14245 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h14239 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14245 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)
DMCXN946_cm33_core1.h14239 #define DIGTMP_PPR_TPP4_MASK (0x10U) macro
14245 … (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK)