Home
last modified time | relevance | path

Searched refs:DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_dcdc.c268 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
283 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_dcdc.c268 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
283 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_dcdc.c268 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
283 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_dcdc.c268 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
283 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.c362 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.c483 … DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); in DCDC_SetLoopControlConfig()
498 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; in DCDC_SetLoopControlConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h26019 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
26022 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
DMIMXRT1175_cm7.h26022 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
26025 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h25710 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
25713 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
DMIMXRT1165_cm4.h25707 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
25710 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h26022 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
26025 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h27712 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
27715 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
DMIMXRT1166_cm7.h27715 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
27718 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h28021 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
28024 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
DMIMXRT1173_cm7.h28024 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
28027 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h28027 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
28030 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h28029 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
28032 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
DMIMXRT1176_cm4.h28026 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
28029 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h27326 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) macro
27332 …(uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)

12