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Searched refs:CTRL2 (Results 1 – 25 of 179) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/qdc/
Dfsl_qdc.c149 …tmp16 = base->CTRL2 & (uint16_t)(~(QDC_CTRL2_W1C_FLAGS | QDC_CTRL2_OUTCTL_MASK | QDC_CTRL2_REVMOD_… in QDC_Init()
174 base->CTRL2 = tmp16; in QDC_Init()
368 if (0U != (QDC_CTRL2_SABIRQ_MASK & base->CTRL2)) in QDC_GetStatusFlags()
373 if (0U != (QDC_CTRL2_ROIRQ_MASK & base->CTRL2)) in QDC_GetStatusFlags()
377 if (0U != (QDC_CTRL2_RUIRQ_MASK & base->CTRL2)) in QDC_GetStatusFlags()
381 if (0U != (QDC_CTRL2_DIR_MASK & base->CTRL2)) in QDC_GetStatusFlags()
439 base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); in QDC_ClearStatusFlags()
492 base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); in QDC_EnableInterrupts()
545 … base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~QDC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); in QDC_DisableInterrupts()
579 if (0U != (QDC_CTRL2_SABIE_MASK & base->CTRL2)) in QDC_GetEnabledInterrupts()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/enc/
Dfsl_enc.c150 …tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_… in ENC_Init()
175 base->CTRL2 = tmp16; in ENC_Init()
369 if (0U != (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) in ENC_GetStatusFlags()
374 if (0U != (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) in ENC_GetStatusFlags()
378 if (0U != (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) in ENC_GetStatusFlags()
382 if (0U != (ENC_CTRL2_DIR_MASK & base->CTRL2)) in ENC_GetStatusFlags()
440 base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); in ENC_ClearStatusFlags()
493 base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16); in ENC_EnableInterrupts()
546 … base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); in ENC_DisableInterrupts()
580 if (0U != (ENC_CTRL2_SABIE_MASK & base->CTRL2)) in ENC_GetEnabledInterrupts()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/hsadc/
Dfsl_hsadc.c117 tmp16 = (uint16_t)(base->CTRL2 & ~HSADC_CTRL2_SIMULT_MASK); in HSADC_Init()
122 base->CTRL2 = tmp16; in HSADC_Init()
221 tmp16 = (uint16_t)(base->CTRL2 & ~HSADC_CTRL2_DIVA_MASK); in HSADC_SetConverterConfig()
223 base->CTRL2 = tmp16; in HSADC_SetConverterConfig()
327 base->CTRL2 &= ~(uint16_t)HSADC_CTRL2_STOPB_MASK; in HSADC_EnableConverter()
331 base->CTRL2 |= HSADC_CTRL2_STOPB_MASK; in HSADC_EnableConverter()
367 base->CTRL2 |= HSADC_CTRL2_SYNCB_MASK; in HSADC_EnableConverterSyncInput()
371 base->CTRL2 &= ~(uint16_t)HSADC_CTRL2_SYNCB_MASK; in HSADC_EnableConverterSyncInput()
434 base->CTRL2 |= HSADC_CTRL2_STARTB_MASK; in HSADC_DoSoftwareTriggerConverter()
464 base->CTRL2 |= HSADC_CTRL2_DMAENB_MASK; in HSADC_EnableConverterDMA()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/pwm/
Dfsl_pwm.c296 reg = base->SM[subModule].CTRL2; in PWM_Init()
330 base->SM[subModule].CTRL2 = reg; in PWM_Init()
375 base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); in PWM_Init()
1304 uint16_t reg = base->SM[subModule].CTRL2; in PWM_SetPwmForceOutputToZero()
1337 base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; in PWM_SetPwmForceOutputToZero()
1339 base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; in PWM_SetPwmForceOutputToZero()
1341 base->SM[subModule].CTRL2 = reg; in PWM_SetPwmForceOutputToZero()
1359 uint16_t reg = base->SM[subModule].CTRL2; in PWM_SetChannelOutput()
1417 base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; in PWM_SetChannelOutput()
1419 base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; in PWM_SetChannelOutput()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/drivers/eqdc/
Dfsl_eqdc.c144 base->CTRL2 = in EQDC_Init()
279 base->CTRL2 &= ~EQDC_CTRL2_OPMODE_MASK; in EQDC_SetOperateMode()
284 base->CTRL2 |= EQDC_CTRL2_OPMODE_MASK; in EQDC_SetOperateMode()
289 base->CTRL2 &= ~EQDC_CTRL2_OPMODE_MASK; in EQDC_SetOperateMode()
294 base->CTRL2 |= EQDC_CTRL2_OPMODE_MASK; in EQDC_SetOperateMode()
Dfsl_eqdc.h542 base->CTRL2 = (base->CTRL2 & (uint16_t)(~EQDC_CTRL2_CMODE_MASK)) | EQDC_CTRL2_CMODE(countMode); in EQDC_SetCountMode()
630 base->CTRL2 |= EQDC_CTRL2_LDMOD_MASK; in EQDC_SetBufferedRegisterLoadUpdateMode()
644 base->CTRL2 &= ~EQDC_CTRL2_LDMOD_MASK; in EQDC_ClearBufferedRegisterLoadUpdateMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_clock.c1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1174 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1178 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
1190 …(OSC_RC_400M->CTRL2.RW & ~OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK) | OSC_RC_400M_CTRL2_OSC_TUNE_VAL(tu… in CLOCK_OSC_SetOscRc400MTuneValue()
1663 … OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK | OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_TrimOscRc400M()
1664 …OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_OSC_TUNE_VAL(trim) | OSC_RC_400M_CTRL2_TUNE_BYP(bypass); in CLOCK_OSC_TrimOscRc400M()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_clock.c1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1174 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1178 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
1190 …(OSC_RC_400M->CTRL2.RW & ~OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK) | OSC_RC_400M_CTRL2_OSC_TUNE_VAL(tu… in CLOCK_OSC_SetOscRc400MTuneValue()
1663 … OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK | OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_TrimOscRc400M()
1664 …OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_OSC_TUNE_VAL(trim) | OSC_RC_400M_CTRL2_TUNE_BYP(bypass); in CLOCK_OSC_TrimOscRc400M()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_clock.c1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1174 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1178 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
1190 …(OSC_RC_400M->CTRL2.RW & ~OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK) | OSC_RC_400M_CTRL2_OSC_TUNE_VAL(tu… in CLOCK_OSC_SetOscRc400MTuneValue()
1663 … OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK | OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_TrimOscRc400M()
1664 …OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_OSC_TUNE_VAL(trim) | OSC_RC_400M_CTRL2_TUNE_BYP(bypass); in CLOCK_OSC_TrimOscRc400M()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_clock.c1136 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1140 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_BypassOscRc400MTuneLogic()
1155 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1159 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_START_MASK; in CLOCK_OSC_EnableOscRc400MTuneLogic()
1174 OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1178 OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_TUNE_EN_MASK; in CLOCK_OSC_FreezeOscRc400MTuneValue()
1189 OSC_RC_400M->CTRL2.RW = in CLOCK_OSC_SetOscRc400MTuneValue()
1190 …(OSC_RC_400M->CTRL2.RW & ~OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK) | OSC_RC_400M_CTRL2_OSC_TUNE_VAL(tu… in CLOCK_OSC_SetOscRc400MTuneValue()
1663 … OSC_RC_400M->CTRL2.CLR = OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK | OSC_RC_400M_CTRL2_TUNE_BYP_MASK; in CLOCK_OSC_TrimOscRc400M()
1664 …OSC_RC_400M->CTRL2.SET = OSC_RC_400M_CTRL2_OSC_TUNE_VAL(trim) | OSC_RC_400M_CTRL2_TUNE_BYP(bypass); in CLOCK_OSC_TrimOscRc400M()
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.c654 lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); in FLEXCAN_IsMbOccupied()
700 firstValidMbNum = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); in FLEXCAN_GetFirstValidMb()
762 base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; in FLEXCAN_Reset()
766 base->CTRL2 |= CAN_CTRL2_WRMFRZ_MASK; in FLEXCAN_Reset()
773 base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK; in FLEXCAN_Reset()
967 base->CTRL2 |= CAN_CTRL2_ECRWRE_MASK; in FLEXCAN_Init()
978 base->CTRL2 &= ~CAN_CTRL2_ECRWRE_MASK; in FLEXCAN_Init()
1200 base->CTRL2 |= CAN_CTRL2_ISOCANFDEN_MASK; in FLEXCAN_FDInit()
1450 base->CTRL2 |= CAN_CTRL2_BTE_MASK; in FLEXCAN_SetTimingConfig()
1526 base->CTRL2 |= CAN_CTRL2_BTE_MASK; in FLEXCAN_SetFDTimingConfig()
[all …]
Dfsl_flexcan.h1698 base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); in FLEXCAN_EnableInterrupts()
1752 base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); in FLEXCAN_DisableInterrupts()
/hal_nxp-latest/mcux/mcux-sdk/drivers/sfa/
Dfsl_sfa.h329 base->CTRL2 |= (mask & (SFA_CTRL2_FREQ_GT_MAX_IRQ_EN_MASK | SFA_CTRL2_FREQ_LT_MIN_IRQ_EN_MASK)); in SFA_EnableInterrupts()
341 … base->CTRL2 &= ~(mask & (SFA_CTRL2_FREQ_GT_MAX_IRQ_EN_MASK | SFA_CTRL2_FREQ_LT_MIN_IRQ_EN_MASK)); in SFA_DisableInterrupts()
Dfsl_sfa.c478 …base->CTRL2 = (base->CTRL2 & ~SFA_CTRL2_REF_CLK_SEL_MASK) | SFA_CTRL2_REF_CLK_SEL(config->refSelec… in SFA_SetMeasureConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/irtc/
Dfsl_irtc.c171 base->CTRL2 |= RTC_CTRL2_WAKEUP_MODE_MASK; in IRTC_Init()
175 base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; in IRTC_Init()
641 base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; in IRTC_SetTamperParams()
Dfsl_irtc.h634 base->CTRL2 |= RTC_CTRL2_TAMP_CFG_OVER_MASK; in IRTC_SetTamperConfigurationOver()
/hal_nxp-latest/mcux/mcux-sdk/drivers/elcdif/
Dfsl_elcdif.c125 …base->CTRL2 = (base->CTRL2 & ~LCDIF_CTRL2_OUTSTANDING_REQS_MASK) | (LCDIF_CTRL2_OUTSTANDING_REQS(4… in ELCDIF_RgbModeInit()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K118_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K116_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K142W_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K146_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K142_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K144_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member
DS32K144W_FLEXCAN.h91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ member

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