Home
last modified time | relevance | path

Searched refs:CT32BIT4_CAP_PMUX_ID (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_inputmux_connections.h38 #define CT32BIT4_CAP_PMUX_ID 0x640U macro
273 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
274 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
275 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
276 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
277 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
278 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
279 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
280 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_inputmux_connections.h38 #define CT32BIT4_CAP_PMUX_ID 0x640U macro
273 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
274 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
275 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
276 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
277 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
278 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
279 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
280 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_inputmux_connections.h39 #define CT32BIT4_CAP_PMUX_ID 0x640U macro
364 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
365 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
366 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
367 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
368 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
369 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
370 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
371 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
372 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_inputmux_connections.h39 #define CT32BIT4_CAP_PMUX_ID 0x640U macro
364 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
365 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
366 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
367 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
368 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
369 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
370 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
371 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
372 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_inputmux_connections.h39 #define CT32BIT4_CAP_PMUX_ID 0x640U macro
364 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
365 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
366 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
367 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
368 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
369 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
370 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
371 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
372 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_inputmux_connections.h49 #define CT32BIT4_CAP_PMUX_ID 0x680U macro
636 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
637 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
638 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
639 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
640 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
641 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
642 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
643 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
644 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_inputmux_connections.h49 #define CT32BIT4_CAP_PMUX_ID 0x680U macro
636 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
637 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
638 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
639 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
640 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
641 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
642 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
643 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
644 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_inputmux_connections.h49 #define CT32BIT4_CAP_PMUX_ID 0x680U macro
636 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
637 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
638 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
639 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
640 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
641 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
642 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
643 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
644 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
[all …]