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Searched refs:CT32BIT1_CAP_PMUX_ID (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_inputmux_connections.h34 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
188 kINPUTMUX_Gpio0Inp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
189 kINPUTMUX_Gpio1Inp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
190 kINPUTMUX_Gpio12Inp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
191 kINPUTMUX_Gpio13Inp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
192 kINPUTMUX_Gpio14Inp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
193 kINPUTMUX_Gpio21Inp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
194 kINPUTMUX_Gpio24Inp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
195 kINPUTMUX_Gpio25Inp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
196 kINPUTMUX_Gpio37Inp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_inputmux_connections.h34 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
188 kINPUTMUX_Gpio0Inp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
189 kINPUTMUX_Gpio1Inp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
190 kINPUTMUX_Gpio12Inp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
191 kINPUTMUX_Gpio13Inp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
192 kINPUTMUX_Gpio14Inp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
193 kINPUTMUX_Gpio21Inp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
194 kINPUTMUX_Gpio24Inp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
195 kINPUTMUX_Gpio25Inp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
196 kINPUTMUX_Gpio37Inp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_inputmux_connections.h35 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
210 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
211 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
212 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
213 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
214 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
215 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
216 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
217 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
218 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_inputmux_connections.h35 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
210 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
211 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
212 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
213 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
214 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
215 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
216 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
217 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
218 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_inputmux_connections.h36 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
301 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
302 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
303 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
304 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
305 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
306 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
307 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
308 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
309 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_inputmux_connections.h36 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
301 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
302 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
303 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
304 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
305 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
306 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
307 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
308 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
309 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_inputmux_connections.h36 #define CT32BIT1_CAP_PMUX_ID 0x610U macro
301 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
302 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
303 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
304 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
305 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
306 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
307 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
308 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
309 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_inputmux_connections.h46 #define CT32BIT1_CAP_PMUX_ID 0x620U macro
543 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
544 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
545 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
546 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
547 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
548 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
549 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
550 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
551 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_inputmux_connections.h46 #define CT32BIT1_CAP_PMUX_ID 0x620U macro
543 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
544 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
545 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
546 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
547 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
548 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
549 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
550 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
551 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_inputmux_connections.h46 #define CT32BIT1_CAP_PMUX_ID 0x620U macro
543 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
544 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
545 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
546 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
547 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
548 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
549 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
550 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
551 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
[all …]