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Searched refs:CT32BIT0_CAP_PMUX_ID (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_inputmux_connections.h33 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
162 …kINPUTMUX_Gpio0Inp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
163 …kINPUTMUX_Gpio1Inp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
164 …kINPUTMUX_Gpio12Inp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
165 …kINPUTMUX_Gpio13Inp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
166 …kINPUTMUX_Gpio14Inp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
167 …kINPUTMUX_Gpio21Inp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
168 …kINPUTMUX_Gpio24Inp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
169 …kINPUTMUX_Gpio25Inp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
170 …kINPUTMUX_Gpio37Inp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_inputmux_connections.h33 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
162 …kINPUTMUX_Gpio0Inp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
163 …kINPUTMUX_Gpio1Inp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
164 …kINPUTMUX_Gpio12Inp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
165 …kINPUTMUX_Gpio13Inp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
166 …kINPUTMUX_Gpio14Inp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
167 …kINPUTMUX_Gpio21Inp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
168 …kINPUTMUX_Gpio24Inp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
169 …kINPUTMUX_Gpio25Inp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
170 …kINPUTMUX_Gpio37Inp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_inputmux_connections.h34 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
189 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
190 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
191 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
192 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
193 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
194 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
195 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
196 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
197 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_inputmux_connections.h34 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
189 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
190 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
191 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
192 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
193 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
194 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
195 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
196 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
197 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_inputmux_connections.h35 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
280 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
282 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
283 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
284 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
285 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
286 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
287 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
288 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_inputmux_connections.h35 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
280 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
282 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
283 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
284 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
285 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
286 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
287 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
288 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_inputmux_connections.h35 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
280 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
282 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
283 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
284 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
285 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
286 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
287 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
288 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_inputmux_connections.h45 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
512 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
513 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
514 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
515 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
516 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
517 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
518 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
519 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
520 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_inputmux_connections.h45 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
512 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
513 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
514 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
515 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
516 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
517 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
518 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
519 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
520 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_inputmux_connections.h45 #define CT32BIT0_CAP_PMUX_ID 0x600U macro
512 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
513 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
514 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
515 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
516 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
517 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
518 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
519 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
520 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
[all …]