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Searched refs:CLKCTL1 (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.c66 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection); in CLOCK_AttachClk()
96 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name); in CLOCK_SetClkDiv()
243 switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK) in CLOCK_GetAudioPllFreq()
259 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL) in CLOCK_GetAudioPllFreq()
262 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0D… in CLOCK_GetAudioPllFreq()
263 …freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT… in CLOCK_GetAudioPllFreq()
277 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL) in CLOCK_GetAudioPfdFreq()
284 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)); in CLOCK_GetAudioPfdFreq()
290 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)); in CLOCK_GetAudioPfdFreq()
296 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)); in CLOCK_GetAudioPfdFreq()
[all …]
Dfsl_power.c858 dspclk_sel[0] = CLKCTL1->DSPCPUCLKSELA; in POWER_EnterDeepSleep()
859 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in POWER_EnterDeepSleep()
923 CLKCTL1->DSPCPUCLKSELA = CLKCTL1_DSPCPUCLKSELA_SEL(0); in POWER_EnterDeepSleep()
924 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in POWER_EnterDeepSleep()
940 …pfd_need_gate[1] = IS_AUDPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL1->AUDIOPLL0PFD) & AUDIOPLL0PFD_PFD_C… in POWER_EnterDeepSleep()
943 CLKCTL1->AUDIOPLL0PFD |= pfd_need_gate[1]; in POWER_EnterDeepSleep()
946 CLKCTL1->AUDIOPLL0CTL0 |= pll_need_rst[1]; in POWER_EnterDeepSleep()
969 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK); in POWER_EnterDeepSleep()
976 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK); in POWER_EnterDeepSleep()
993 CLKCTL1->AUDIOPLL0PFD &= ~pfd_need_gate[1]; in POWER_EnterDeepSleep()
[all …]
Dfsl_clock.h901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
930 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
933 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
936 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1208 …CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET… in CLOCK_DeinitAudioPll()
1223 …CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd… in CLOCK_DeinitAudioPfd()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.c66 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection); in CLOCK_AttachClk()
96 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name); in CLOCK_SetClkDiv()
243 switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK) in CLOCK_GetAudioPllFreq()
259 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL) in CLOCK_GetAudioPllFreq()
262 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0D… in CLOCK_GetAudioPllFreq()
263 …freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT… in CLOCK_GetAudioPllFreq()
277 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL) in CLOCK_GetAudioPfdFreq()
284 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)); in CLOCK_GetAudioPfdFreq()
290 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)); in CLOCK_GetAudioPfdFreq()
296 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)); in CLOCK_GetAudioPfdFreq()
[all …]
Dfsl_power.c858 dspclk_sel[0] = CLKCTL1->DSPCPUCLKSELA; in POWER_EnterDeepSleep()
859 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in POWER_EnterDeepSleep()
923 CLKCTL1->DSPCPUCLKSELA = CLKCTL1_DSPCPUCLKSELA_SEL(0); in POWER_EnterDeepSleep()
924 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in POWER_EnterDeepSleep()
940 …pfd_need_gate[1] = IS_AUDPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL1->AUDIOPLL0PFD) & AUDIOPLL0PFD_PFD_C… in POWER_EnterDeepSleep()
943 CLKCTL1->AUDIOPLL0PFD |= pfd_need_gate[1]; in POWER_EnterDeepSleep()
946 CLKCTL1->AUDIOPLL0CTL0 |= pll_need_rst[1]; in POWER_EnterDeepSleep()
969 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK); in POWER_EnterDeepSleep()
976 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK); in POWER_EnterDeepSleep()
993 CLKCTL1->AUDIOPLL0PFD &= ~pfd_need_gate[1]; in POWER_EnterDeepSleep()
[all …]
Dfsl_clock.h901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
904 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
907 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
930 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
933 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
936 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1208 …CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET… in CLOCK_DeinitAudioPll()
1223 …CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd… in CLOCK_DeinitAudioPfd()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.c62 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, tuple); in CLOCK_AttachClk()
97 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name); in CLOCK_SetClkDiv()
225 switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK) in CLOCK_GetAudioPllFreq()
238 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetAudioPllFreq()
241 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0D… in CLOCK_GetAudioPllFreq()
242 …freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT… in CLOCK_GetAudioPllFreq()
258 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetAudioPfdFreq()
265 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)); in CLOCK_GetAudioPfdFreq()
271 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)); in CLOCK_GetAudioPfdFreq()
277 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)); in CLOCK_GetAudioPfdFreq()
[all …]
Dfsl_power.c898 dspclk_sel[0] = CLKCTL1->DSPCPUCLKSELA; in AT_QUICKACCESS_SECTION_CODE()
899 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
1017 CLKCTL1->DSPCPUCLKSELA = CLKCTL1_DSPCPUCLKSELA_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1018 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1034 …pfd_need_gate[1] = IS_AUDPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL1->AUDIOPLL0PFD) & AUDIOPLL0PFD_PFD_C… in AT_QUICKACCESS_SECTION_CODE()
1037 CLKCTL1->AUDIOPLL0PFD |= pfd_need_gate[1]; in AT_QUICKACCESS_SECTION_CODE()
1040 CLKCTL1->AUDIOPLL0CTL0 |= pll_need_rst[1]; in AT_QUICKACCESS_SECTION_CODE()
1064 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK); in AT_QUICKACCESS_SECTION_CODE()
1072 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK); in AT_QUICKACCESS_SECTION_CODE()
1090 CLKCTL1->AUDIOPLL0PFD &= ~pfd_need_gate[1]; in AT_QUICKACCESS_SECTION_CODE()
[all …]
Dfsl_clock.h1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1143 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1149 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1480 …CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET… in CLOCK_DeinitAudioPll()
1497 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8U * pfd)); in CLOCK_DeinitAudioPfd()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.c62 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, tuple); in CLOCK_AttachClk()
97 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name); in CLOCK_SetClkDiv()
225 switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK) in CLOCK_GetAudioPllFreq()
238 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetAudioPllFreq()
241 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0D… in CLOCK_GetAudioPllFreq()
242 …freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT… in CLOCK_GetAudioPllFreq()
258 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetAudioPfdFreq()
265 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)); in CLOCK_GetAudioPfdFreq()
271 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)); in CLOCK_GetAudioPfdFreq()
277 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)); in CLOCK_GetAudioPfdFreq()
[all …]
Dfsl_power.c898 dspclk_sel[0] = CLKCTL1->DSPCPUCLKSELA; in AT_QUICKACCESS_SECTION_CODE()
899 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
1017 CLKCTL1->DSPCPUCLKSELA = CLKCTL1_DSPCPUCLKSELA_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1018 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1034 …pfd_need_gate[1] = IS_AUDPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL1->AUDIOPLL0PFD) & AUDIOPLL0PFD_PFD_C… in AT_QUICKACCESS_SECTION_CODE()
1037 CLKCTL1->AUDIOPLL0PFD |= pfd_need_gate[1]; in AT_QUICKACCESS_SECTION_CODE()
1040 CLKCTL1->AUDIOPLL0CTL0 |= pll_need_rst[1]; in AT_QUICKACCESS_SECTION_CODE()
1064 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK); in AT_QUICKACCESS_SECTION_CODE()
1072 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK); in AT_QUICKACCESS_SECTION_CODE()
1090 CLKCTL1->AUDIOPLL0PFD &= ~pfd_need_gate[1]; in AT_QUICKACCESS_SECTION_CODE()
[all …]
Dfsl_clock.h1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1143 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1149 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1480 …CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET… in CLOCK_DeinitAudioPll()
1497 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8U * pfd)); in CLOCK_DeinitAudioPfd()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.c62 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, tuple); in CLOCK_AttachClk()
97 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name); in CLOCK_SetClkDiv()
225 switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK) in CLOCK_GetAudioPllFreq()
238 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetAudioPllFreq()
241 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0D… in CLOCK_GetAudioPllFreq()
242 …freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT… in CLOCK_GetAudioPllFreq()
258 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetAudioPfdFreq()
265 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT)); in CLOCK_GetAudioPfdFreq()
271 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT)); in CLOCK_GetAudioPfdFreq()
277 … ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT)); in CLOCK_GetAudioPfdFreq()
[all …]
Dfsl_power.c898 dspclk_sel[0] = CLKCTL1->DSPCPUCLKSELA; in AT_QUICKACCESS_SECTION_CODE()
899 dspclk_sel[1] = CLKCTL1->DSPCPUCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
1017 CLKCTL1->DSPCPUCLKSELA = CLKCTL1_DSPCPUCLKSELA_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1018 CLKCTL1->DSPCPUCLKSELB = CLKCTL1_DSPCPUCLKSELB_SEL(0); in AT_QUICKACCESS_SECTION_CODE()
1034 …pfd_need_gate[1] = IS_AUDPLL_ON(pll_need_pd) ? 0U : ((~CLKCTL1->AUDIOPLL0PFD) & AUDIOPLL0PFD_PFD_C… in AT_QUICKACCESS_SECTION_CODE()
1037 CLKCTL1->AUDIOPLL0PFD |= pfd_need_gate[1]; in AT_QUICKACCESS_SECTION_CODE()
1040 CLKCTL1->AUDIOPLL0CTL0 |= pll_need_rst[1]; in AT_QUICKACCESS_SECTION_CODE()
1064 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_RESET_MASK); in AT_QUICKACCESS_SECTION_CODE()
1072 CLKCTL1->AUDIOPLL0CTL0 &= ~(pll_need_rst[1] & CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK); in AT_QUICKACCESS_SECTION_CODE()
1090 CLKCTL1->AUDIOPLL0PFD &= ~pfd_need_gate[1]; in AT_QUICKACCESS_SECTION_CODE()
[all …]
Dfsl_clock.h1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1117 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1120 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1143 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1146 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1149 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
1480 …CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET… in CLOCK_DeinitAudioPll()
1497 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8U * pfd)); in CLOCK_DeinitAudioPfd()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.c280 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
283 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
286 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
334 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
337 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
340 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
370 CLKCTL1->CLKOUTSEL0 = CLKCTL1_CLKOUTSEL0_SEL(((uint32_t)connection >> 4U) & 0x7U); in CLOCK_AttachClk()
371 CLKCTL1->CLKOUTSEL1 = CLKCTL1_CLKOUTSEL1_SEL(((uint32_t)connection >> 8U) & 0x7U); in CLOCK_AttachClk()
372 CLKCTL1->CLKOUTSEL2 = CLKCTL1_CLKOUTSEL2_SEL(((uint32_t)connection >> 12U) & 0x7U); in CLOCK_AttachClk()
383 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection); in CLOCK_AttachClk()
[all …]
Dfsl_power.c837 uint32_t rtcClk = CLKCTL1->PSCCTL2 & CLKCTL1_PSCCTL2_RTC_LITE_MASK; in AT_QUICKACCESS_SECTION_CODE()
934 CLKCTL1->PSCCTL2_SET = rtcClk; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.c280 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
283 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
286 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
334 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
337 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
340 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
370 CLKCTL1->CLKOUTSEL0 = CLKCTL1_CLKOUTSEL0_SEL(((uint32_t)connection >> 4U) & 0x7U); in CLOCK_AttachClk()
371 CLKCTL1->CLKOUTSEL1 = CLKCTL1_CLKOUTSEL1_SEL(((uint32_t)connection >> 8U) & 0x7U); in CLOCK_AttachClk()
372 CLKCTL1->CLKOUTSEL2 = CLKCTL1_CLKOUTSEL2_SEL(((uint32_t)connection >> 12U) & 0x7U); in CLOCK_AttachClk()
383 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection); in CLOCK_AttachClk()
[all …]
Dfsl_power.c837 uint32_t rtcClk = CLKCTL1->PSCCTL2 & CLKCTL1_PSCCTL2_RTC_LITE_MASK; in AT_QUICKACCESS_SECTION_CODE()
934 CLKCTL1->PSCCTL2_SET = rtcClk; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_dsp.c104 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
107 switch ((CLKCTL1->DSPCPUCLKSELA) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
151 SystemCoreClock = freq / ((CLKCTL1->DSPCPUCLKDIV & 0xFFU) + 1U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_dsp.c130 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
133 switch ((CLKCTL1->DSPCPUCLKSELA) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
178 SystemCoreClock = freq / ((CLKCTL1->DSPCPUCLKDIV & 0xffU) + 1U); in SystemCoreClockUpdate()
DMIMXRT685S_cm33.h10299 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
10305 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
10314 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
10318 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h10299 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
10305 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
10314 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
10318 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h12458 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
12464 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
12473 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
12477 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h12461 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
12467 #define CLKCTL1_BASE_PTRS { CLKCTL1 }
12476 #define CLKCTL1 ((CLKCTL1_Type *)CLKCTL1_BASE) macro
12480 #define CLKCTL1_BASE_PTRS { CLKCTL1 }

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