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Searched refs:CLKCTL0 (Results 1 – 25 of 53) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.c66 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, tuple); in CLOCK_AttachClk()
80 CLKCTL0->FRODIVSEL = (((uint32_t)connection) >> 28U) & 0x3U; in CLOCK_AttachClk()
101 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name); in CLOCK_SetClkDiv()
129 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in CLOCK_GetSysPllFreq()
142 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPllFreq()
145 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in CLOCK_GetSysPllFreq()
146 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in CLOCK_GetSysPllFreq()
162 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPfdFreq()
169 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in CLOCK_GetSysPfdFreq()
175 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); in CLOCK_GetSysPfdFreq()
[all …]
Dfsl_power.c630 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
642 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
704 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
711 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
895 frodiv_sel = CLKCTL0->FRODIVSEL; in AT_QUICKACCESS_SECTION_CODE()
896 mainclk_sel[0] = CLKCTL0->MAINCLKSELA; in AT_QUICKACCESS_SECTION_CODE()
897 mainclk_sel[1] = CLKCTL0->MAINCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
900 cpu_div = CLKCTL0->SYSCPUAHBCLKDIV; in AT_QUICKACCESS_SECTION_CODE()
973 while ((CLKCTL0->LPOSCCTL0 & CLKCTL0_LPOSCCTL0_CLKRDY_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
980 fro_oen = CLKCTL0->FRODIVOEN; in AT_QUICKACCESS_SECTION_CODE()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.c66 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, tuple); in CLOCK_AttachClk()
80 CLKCTL0->FRODIVSEL = (((uint32_t)connection) >> 28U) & 0x3U; in CLOCK_AttachClk()
101 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name); in CLOCK_SetClkDiv()
129 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in CLOCK_GetSysPllFreq()
142 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPllFreq()
145 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in CLOCK_GetSysPllFreq()
146 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in CLOCK_GetSysPllFreq()
162 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPfdFreq()
169 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in CLOCK_GetSysPfdFreq()
175 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); in CLOCK_GetSysPfdFreq()
[all …]
Dfsl_power.c630 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
642 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
704 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
711 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
895 frodiv_sel = CLKCTL0->FRODIVSEL; in AT_QUICKACCESS_SECTION_CODE()
896 mainclk_sel[0] = CLKCTL0->MAINCLKSELA; in AT_QUICKACCESS_SECTION_CODE()
897 mainclk_sel[1] = CLKCTL0->MAINCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
900 cpu_div = CLKCTL0->SYSCPUAHBCLKDIV; in AT_QUICKACCESS_SECTION_CODE()
973 while ((CLKCTL0->LPOSCCTL0 & CLKCTL0_LPOSCCTL0_CLKRDY_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
980 fro_oen = CLKCTL0->FRODIVOEN; in AT_QUICKACCESS_SECTION_CODE()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.c66 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, tuple); in CLOCK_AttachClk()
80 CLKCTL0->FRODIVSEL = (((uint32_t)connection) >> 28U) & 0x3U; in CLOCK_AttachClk()
101 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name); in CLOCK_SetClkDiv()
129 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in CLOCK_GetSysPllFreq()
142 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPllFreq()
145 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in CLOCK_GetSysPllFreq()
146 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in CLOCK_GetSysPllFreq()
162 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPfdFreq()
169 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in CLOCK_GetSysPfdFreq()
175 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); in CLOCK_GetSysPfdFreq()
[all …]
Dfsl_power.c630 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
642 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
704 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
711 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
895 frodiv_sel = CLKCTL0->FRODIVSEL; in AT_QUICKACCESS_SECTION_CODE()
896 mainclk_sel[0] = CLKCTL0->MAINCLKSELA; in AT_QUICKACCESS_SECTION_CODE()
897 mainclk_sel[1] = CLKCTL0->MAINCLKSELB; in AT_QUICKACCESS_SECTION_CODE()
900 cpu_div = CLKCTL0->SYSCPUAHBCLKDIV; in AT_QUICKACCESS_SECTION_CODE()
973 while ((CLKCTL0->LPOSCCTL0 & CLKCTL0_LPOSCCTL0_CLKRDY_MASK) == 0U) in AT_QUICKACCESS_SECTION_CODE()
980 fro_oen = CLKCTL0->FRODIVOEN; in AT_QUICKACCESS_SECTION_CODE()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.c70 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection); in CLOCK_AttachClk()
100 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name); in CLOCK_SetClkDiv()
125 switch ((CLKCTL0->FFROCTL0) & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) in CLOCK_GetFFroFreq()
148 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in CLOCK_GetSysPllFreq()
164 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPllFreq()
167 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in CLOCK_GetSysPllFreq()
168 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in CLOCK_GetSysPllFreq()
182 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPfdFreq()
189 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in CLOCK_GetSysPfdFreq()
195 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); in CLOCK_GetSysPfdFreq()
[all …]
Dfsl_power.c139 #define US2LOOP(x) ((x) * ((CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) == 0U ? 3U : 4U))
633 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
703 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
814 temp = (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) == 0U ? 12U : 15U; in AT_QUICKACCESS_SECTION_CODE()
856 mainclk_sel[0] = CLKCTL0->MAINCLKSELA; in POWER_EnterDeepSleep()
857 mainclk_sel[1] = CLKCTL0->MAINCLKSELB; in POWER_EnterDeepSleep()
860 cpu_div = CLKCTL0->SYSCPUAHBCLKDIV; in POWER_EnterDeepSleep()
921 CLKCTL0->MAINCLKSELA = CLKCTL0_MAINCLKSELA_SEL(0); in POWER_EnterDeepSleep()
922 CLKCTL0->MAINCLKSELB = CLKCTL0_MAINCLKSELB_SEL(0); in POWER_EnterDeepSleep()
925 CLKCTL0->SYSCPUAHBCLKDIV = 0; in POWER_EnterDeepSleep()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.c70 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection); in CLOCK_AttachClk()
100 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name); in CLOCK_SetClkDiv()
125 switch ((CLKCTL0->FFROCTL0) & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) in CLOCK_GetFFroFreq()
148 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in CLOCK_GetSysPllFreq()
164 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPllFreq()
167 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in CLOCK_GetSysPllFreq()
168 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in CLOCK_GetSysPllFreq()
182 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in CLOCK_GetSysPfdFreq()
189 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in CLOCK_GetSysPfdFreq()
195 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); in CLOCK_GetSysPfdFreq()
[all …]
Dfsl_power.c139 #define US2LOOP(x) ((x) * ((CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) == 0U ? 3U : 4U))
633 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
703 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
814 temp = (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) == 0U ? 12U : 15U; in AT_QUICKACCESS_SECTION_CODE()
856 mainclk_sel[0] = CLKCTL0->MAINCLKSELA; in POWER_EnterDeepSleep()
857 mainclk_sel[1] = CLKCTL0->MAINCLKSELB; in POWER_EnterDeepSleep()
860 cpu_div = CLKCTL0->SYSCPUAHBCLKDIV; in POWER_EnterDeepSleep()
921 CLKCTL0->MAINCLKSELA = CLKCTL0_MAINCLKSELA_SEL(0); in POWER_EnterDeepSleep()
922 CLKCTL0->MAINCLKSELB = CLKCTL0_MAINCLKSELB_SEL(0); in POWER_EnterDeepSleep()
925 CLKCTL0->SYSCPUAHBCLKDIV = 0; in POWER_EnterDeepSleep()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_dsp.c52 …return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT… in getOscClk()
60 switch (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) in getFFroFreq()
80 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in getSpllFreq()
96 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in getSpllFreq()
99 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in getSpllFreq()
100 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in getSpllFreq()
154 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
156 … freq = (uint32_t)((uint64_t)freq * 18U / ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> in SystemCoreClockUpdate()
159 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
163 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
[all …]
Dsystem_MIMXRT685S_cm33.c62 …return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT… in getOscClk()
70 switch (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) in getFFroFreq()
149 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
152 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
175 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in SystemCoreClockUpdate()
191 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
194 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in SystemCoreClockUpdate()
195 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in SystemCoreClockUpdate()
198 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
200 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
Dsystem_MIMXRT633S.c61 …return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT… in getOscClk()
69 switch (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) in getFFroFreq()
148 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
151 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
174 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in SystemCoreClockUpdate()
190 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
193 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in SystemCoreClockUpdate()
194 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in SystemCoreClockUpdate()
197 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
199 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_dsp.c57 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in getSpllFreq()
70 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in getSpllFreq()
73 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in getSpllFreq()
74 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in getSpllFreq()
125 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
129 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
131 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
135 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
139 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); in SystemCoreClockUpdate()
141 freq = freq / ((CLKCTL0->DSPPLLCLKDIV & CLKCTL0_DSPPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
Dsystem_MIMXRT595S_cm33.c66 switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK) in getFroDivClk()
160 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
163 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
184 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in SystemCoreClockUpdate()
197 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
200 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in SystemCoreClockUpdate()
201 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in SystemCoreClockUpdate()
205 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
208 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
220 SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.c271 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
274 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
277 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
325 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
328 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
331 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
387 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection); in CLOCK_AttachClk()
417 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, name); in CLOCK_SetClkDiv()
520 …return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U… in CLOCK_GetMainPllClkFreq()
525 …return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U… in CLOCK_GetAux0PllClkFreq()
[all …]
Dfsl_power.c616 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK; in AT_QUICKACCESS_SECTION_CODE()
686 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in AT_QUICKACCESS_SECTION_CODE()
835 uint32_t clk = CLKCTL0->PSCCTL0; in AT_QUICKACCESS_SECTION_CODE()
840 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK; in AT_QUICKACCESS_SECTION_CODE()
932 CLKCTL0->PSCCTL0 = clk; in AT_QUICKACCESS_SECTION_CODE()
1040 reg = CLKCTL0->PSCCTL0; in POWER_InitPowerConfig()
1041 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_USB_MASK; in POWER_InitPowerConfig()
1045 CLKCTL0->PSCCTL0 = reg; in POWER_InitPowerConfig()
1048 CLKCTL0->G2BIST_CLK_EN = 0U; in POWER_InitPowerConfig()
1276 pscctl0 = CLKCTL0->PSCCTL0; in POWER_DisableGDetVSensors()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.c271 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
274 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
277 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
325 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
328 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
331 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_DisableClock()
387 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection); in CLOCK_AttachClk()
417 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, name); in CLOCK_SetClkDiv()
520 …return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U… in CLOCK_GetMainPllClkFreq()
525 …return CLOCK_GetTcpuMciClkFreq() / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U… in CLOCK_GetAux0PllClkFreq()
[all …]
Dfsl_power.c616 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK; in AT_QUICKACCESS_SECTION_CODE()
686 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in AT_QUICKACCESS_SECTION_CODE()
835 uint32_t clk = CLKCTL0->PSCCTL0; in AT_QUICKACCESS_SECTION_CODE()
840 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK; in AT_QUICKACCESS_SECTION_CODE()
932 CLKCTL0->PSCCTL0 = clk; in AT_QUICKACCESS_SECTION_CODE()
1040 reg = CLKCTL0->PSCCTL0; in POWER_InitPowerConfig()
1041 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_USB_MASK; in POWER_InitPowerConfig()
1045 CLKCTL0->PSCCTL0 = reg; in POWER_InitPowerConfig()
1048 CLKCTL0->G2BIST_CLK_EN = 0U; in POWER_InitPowerConfig()
1276 pscctl0 = CLKCTL0->PSCCTL0; in POWER_DisableGDetVSensors()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
Dsystem_MIMXRT555S.c65 switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK) in getFroDivClk()
159 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
162 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
183 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in SystemCoreClockUpdate()
196 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
199 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in SystemCoreClockUpdate()
200 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in SystemCoreClockUpdate()
204 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
207 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
219 SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
Dsystem_MIMXRT533S.c65 switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK) in getFroDivClk()
159 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK) in SystemCoreClockUpdate()
162 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK) in SystemCoreClockUpdate()
183 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) in SystemCoreClockUpdate()
196 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) in SystemCoreClockUpdate()
199 …freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM… in SystemCoreClockUpdate()
200 …freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; in SystemCoreClockUpdate()
204 … ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); in SystemCoreClockUpdate()
207 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
219 SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U); in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt595/
Dclock_config.c74 CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src); in BOARD_SetFlexspiClock()
75 … CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK; /* Reset the divider counter */ in BOARD_SetFlexspiClock()
76 CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1); in BOARD_SetFlexspiClock()
77 while ((CLKCTL0->FLEXSPI0FCLKDIV) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK) in BOARD_SetFlexspiClock()
83 CLKCTL0->FLEXSPI1FCLKSEL = CLKCTL0_FLEXSPI1FCLKSEL_SEL(src); in BOARD_SetFlexspiClock()
84 … CLKCTL0->FLEXSPI1FCLKDIV |= CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK; /* Reset the divider counter */ in BOARD_SetFlexspiClock()
85 CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1); in BOARD_SetFlexspiClock()
86 while ((CLKCTL0->FLEXSPI1FCLKDIV) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK) in BOARD_SetFlexspiClock()
Dboard.c294 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in BOARD_DeinitFlash()
365 if ((CLKCTL0->FLEXSPI0FCLKSEL != CLKCTL0_FLEXSPI0FCLKSEL_SEL(src)) || in BOARD_SetFlexspiClock()
366 ((CLKCTL0->FLEXSPI0FCLKDIV & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK) != (divider - 1))) in BOARD_SetFlexspiClock()
374 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK; in BOARD_SetFlexspiClock()
376 CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src); in BOARD_SetFlexspiClock()
377 … CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK; /* Reset the divider counter */ in BOARD_SetFlexspiClock()
378 CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1); in BOARD_SetFlexspiClock()
379 while ((CLKCTL0->FLEXSPI0FCLKDIV) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK) in BOARD_SetFlexspiClock()
383 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in BOARD_SetFlexspiClock()
390 if ((CLKCTL0->FLEXSPI1FCLKSEL != CLKCTL0_FLEXSPI1FCLKSEL_SEL(src)) || in BOARD_SetFlexspiClock()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmrw612/
Dboard.c211 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in BOARD_DeinitFlash()
285 if ((CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src)) || in BOARD_SetFlexspiClock()
286 ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1))) in BOARD_SetFlexspiClock()
294 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK; in BOARD_SetFlexspiClock()
296 CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src); in BOARD_SetFlexspiClock()
297 … CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */ in BOARD_SetFlexspiClock()
298 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1); in BOARD_SetFlexspiClock()
299 while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) in BOARD_SetFlexspiClock()
303 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in BOARD_SetFlexspiClock()
321 CLKCTL0->ELS_GDET_CLK_SEL = CLKCTL0_ELS_GDET_CLK_SEL_SEL(2); in LoadGdetCfg()
/hal_nxp-latest/mcux/mcux-sdk/boards/rdrw612bga/
Dboard.c304 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in BOARD_DeinitFlash()
378 if ((CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src)) || in BOARD_SetFlexspiClock()
379 ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1))) in BOARD_SetFlexspiClock()
387 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK; in BOARD_SetFlexspiClock()
389 CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src); in BOARD_SetFlexspiClock()
390 … CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */ in BOARD_SetFlexspiClock()
391 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1); in BOARD_SetFlexspiClock()
392 while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK) in BOARD_SetFlexspiClock()
396 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in BOARD_SetFlexspiClock()
414 CLKCTL0->ELS_GDET_CLK_SEL = CLKCTL0_ELS_GDET_CLK_SEL_SEL(2); in LoadGdetCfg()

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