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Searched refs:CLCR (Results 1 – 25 of 52) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/cm33/
Dfsl_cache.c145 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(1) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_InvalidateCacheByRange()
146 base->CLCR = pccReg; in XCACHE_InvalidateCacheByRange()
212 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(2) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanCacheByRange()
213 base->CLCR = pccReg; in XCACHE_CleanCacheByRange()
280 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(3) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanInvalidateCacheByRange()
281 base->CLCR = pccReg; in XCACHE_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/cm33/
Dfsl_cache.c145 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(1) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_InvalidateCacheByRange()
146 base->CLCR = pccReg; in XCACHE_InvalidateCacheByRange()
212 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(2) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanCacheByRange()
213 base->CLCR = pccReg; in XCACHE_CleanCacheByRange()
280 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(3) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanInvalidateCacheByRange()
281 base->CLCR = pccReg; in XCACHE_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/cm33/
Dfsl_cache.c145 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(1) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_InvalidateCacheByRange()
146 base->CLCR = pccReg; in XCACHE_InvalidateCacheByRange()
212 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(2) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanCacheByRange()
213 base->CLCR = pccReg; in XCACHE_CleanCacheByRange()
280 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(3) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanInvalidateCacheByRange()
281 base->CLCR = pccReg; in XCACHE_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/xcache/
Dfsl_cache.c145 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(1) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_InvalidateCacheByRange()
146 base->CLCR = pccReg; in XCACHE_InvalidateCacheByRange()
212 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(2) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanCacheByRange()
213 base->CLCR = pccReg; in XCACHE_CleanCacheByRange()
280 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(3) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanInvalidateCacheByRange()
281 base->CLCR = pccReg; in XCACHE_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/cm33/
Dfsl_cache.c145 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(1) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_InvalidateCacheByRange()
146 base->CLCR = pccReg; in XCACHE_InvalidateCacheByRange()
212 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(2) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanCacheByRange()
213 base->CLCR = pccReg; in XCACHE_CleanCacheByRange()
280 …pccReg = (base->CLCR & ~XCACHE_CLCR_LCMD_MASK) | XCACHE_CLCR_LCMD(3) | XCACHE_CLCR_LADSEL_MASK; in XCACHE_CleanInvalidateCacheByRange()
281 base->CLCR = pccReg; in XCACHE_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c263 …pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CL… in CACHE64_InvalidateCacheByRange()
264 base->CLCR = pccReg; in CACHE64_InvalidateCacheByRange()
333 …pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CL… in CACHE64_CleanCacheByRange()
334 base->CLCR = pccReg; in CACHE64_CleanCacheByRange()
405 …pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CL… in CACHE64_CleanInvalidateCacheByRange()
406 base->CLCR = pccReg; in CACHE64_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h914 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
DMIMXRT685S_cm33.h6222 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16616 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
90573 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
DMIMXRT798S_cm33_core0.h16659 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
90669 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
DMIMXRT798S_ezhv.h16198 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
95893 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16198 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
92097 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
DMIMXRT735S_cm33_core0.h16659 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
87444 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16659 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
90669 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
DMIMXRT758S_ezhv.h16198 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
95869 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6222 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1270 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
DMIMXRT595S_cm33.h7418 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2724 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2724 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7414 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7417 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2723 …__IO uint32_t CLCR; /**< Cache line control register, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h7977 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h7977 __IO uint32_t CLCR; /**< Cache Line Control, offset: 0x804 */ member

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