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Searched refs:CACHE64_POLSEL_POLSEL_REG0_POLICY (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1172 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMIMXRT685S_cm33.h6514 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6514 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1541 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMIMXRT595S_cm33.h7731 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h3025 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h3025 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7727 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7730 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h3024 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8290 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMCXN546_cm33_core1.h8290 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8290 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMCXN547_cm33_core1.h8290 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16914 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMIMXRT798S_cm33_core0.h16973 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMIMXRT798S_ezhv.h16474 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16474 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMIMXRT735S_cm33_core0.h16973 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16973 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8324 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMCXN947_cm33_core0.h8324 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8324 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
DMCXN946_cm33_core1.h8324 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13529 #define CACHE64_POLSEL_POLSEL_REG0_POLICY(x) (((uint32_t)(((uint32_t)(x)) << CACHE64_POLSEL_POL… macro

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